LAN8820 Datasheet, PDF(20/83 Page) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

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LAN8820 Datasheet, PDF (20/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

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LAN8820/LAN8820I

3.3.1 MII ISOLATE MODE

The device may be configured to electrically isolate the RGMII pins by setting the Isolate bit of the Basic Control Reg-

ister. In this mode, all MAC data interface output pins are HIGH and all MAC data interface input pins are ignored. In

this mode, the SMI interface is kept active, allowing the MAC to access the SMI registers and generate interrupts. All

MDI operations are halted while in isolate mode.

3.4 Serial Management Interface (SMI)

The Serial Management Interface is used to control the device and obtain its status. This interface supports the standard

PHY registers required by Clause 22 of the 802.3 standard, as well as âvendor-specificâ registers allowed by the spec-

ification. Non-supported registers (such as 11 to 14) will be read as hexadecimal âFFFFâ. Device registers are detailed

in Section 4.0, "Register Descriptions," on page 34.

At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock provided by the

station management controller (SMC). MDIO is a bi-directional data SMI input/output signal that receives serial data

(commands) from the controller SMC and sends serial data (status) to the SMC. The minimum time between edges of

the MDC is 160 ns. There is no maximum time between edges. The minimum cycle time (time between two consecutive

rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily

driven by the I/O port of a microcontroller.

The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing of the data is shown

in Figure 1-1 and Figure 1-2. The timing relationships of the MDIO signals are further described in Section 5.5.6, "SMI

Timing," on page 73.

FIGURE 3-4:

MDIO TIMING AND FRAME STRUCTURE - READ CYCLE

Read Cycle

MDC

MDIO 32 1's 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

D15 D14

Preamble

Start of

Frame

Code

PHY Address

Turn

Around

...

Data

D1 D0

Data To Phy

Data From Phy

FIGURE 3-5:

MDIO TIMING AND FRAME STRUCTURE - WRITE CYCLE

Write Cycle

MDC

MDIO 32 1's 0 1