LAN8820 Datasheet, PDF (47/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

LAN8820/LAN8820I
Bits
Description
Type
4:0 PHYADD[4:0]
R/W
The PHY Address is used for the SMI address and for the initialization of the _NASR
Cipher (Scrambler) key.
Default
Note 4-6
Note 4-6
The default is determined by the CONFIG[1:0] pins as described in Section 3.8.1.2.1, "Configuring
the SMI Address (CONFIG[1:0])," on page 25.
4.2.16 EXTENDED MODE CONTROL/STATUS REGISTER
Index (In Decimal): 19
Size:
16 bits
Bits
15:11
10:9
8:3
2
1
0
Description
MOD
Configures mode of operation. Refer to Section 3.8.1.2.2, "Configuring the
Mode of Operation (CONFIG[3:2])," on page 26 for details.
Note: The MOD bits should not be modified and must be preserved
when writing to this register.
Transmitter FIFO Depth
00 = 4 bytes
01 = 5 bytes
10 = 6 bytes
11 = 7 bytes
RESERVED
These bits must be written as 011111b.
MDI/MDI-X 0:1
Selects between MDI and MDI-X for channel 0 and channel 1 only if the Auto
MDIX Disable bit of the 10/100 Mode Control/Status Register is 1.
0 = MDI
1 = MDI-X
MDI/MDI-X 2:3
Selects between MDI and MDI-X for channel 2 and channel 3 only if the Auto
MDIX Disable bit of the 10/100 Mode Control/Status Register is 1.
0 = MDI
1 = MDI-X
CONDITIONAL PARALLEL DETECT
0 = Parallel detect. (Auto Negotiation Advertisement Register is ignored.)
1 = Conditional Parallel Detect only at the speed advertised in the Auto
Negotiation Advertisement Register.
10BASE-T half duplex (10BASE-T bit =1)
100BASE-TX half duplex (100BASE-TX bit =1)
Type
R/W
NASR
R/W
RW
RW
RW
Default
Note 4-7
00b
0b
0b
0b
Note 4-7
The default mode is determined by the CONFIG[3:2] pins as described in Section 3.8.1.2.2,
"Configuring the Mode of Operation (CONFIG[3:2])," on page 26
 2009-2015 Microchip Technology Inc.
DS00001871B-page 47