LAN8820 Datasheet, PDF (31/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

LAN8820/LAN8820I
3.9.8.3 Receive Error-Free Packets Counter
The quality of a link can be monitored by using the Receive Error-Free Packets Counter. The device counts the number
of good packets received and reports a 48-bit value across 3 advanced registers: Receive Error-Free Packets Counter
Low Register, Receive Error-Free Packets Counter Mid Register, and Receive Error-Free Packets Counter High Reg-
ister. The Receive Error-Free Packets Counter Low Register latches the two other related counter registers and must
always be read first. The Receive Error-Free Packets Counter High Register register must be read last, and will auto-
matically clear the counter.
3.9.8.4 CRC Error Counter
This 48-bit counter counts the number of CRC errors detected. It’s value can be read across 3 advanced registers: CRC
Error Counter Low Register, CRC Error Counter Mid Register, and CRC Error Counter High Register. The CRC Error
Counter Low Register latches the two other related counter registers and must always be read first. The CRC Error
Counter High Register must be read last, and will automatically clear the counter.
3.9.8.5 Receive Error During Data Counter
This 16-bit counter counts the number of errors that occurred while data was being received. The value is read from the
Receive Error During Data Counter Register.
3.9.8.6 Receive Error During Idle Counter
This 16-bit counter counts the number of errors that occurred during idle. The value is read from the Receive Error
During Idle Counter Register register.
3.9.8.7 Transmitted Packets Counter
This 48-bit counter counts the number of packets that were transmitted. It’s value can be read across 3 advanced reg-
isters: Transmit Packet Counter Low Register, Transmit Packet Counter Mid Register, and Transmit Packet Counter
High Register. The Transmit Packet Counter Low Register latches the two other related counter registers and must
always be read first. The Transmit Packet Counter High Register must be read last, and it will automatically clear the
counter.
3.10 Application Diagrams
This section provides typical application diagrams for the following:
• Simplified Application Diagram
• Power Supply & Twisted Pair Interface Diagram
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DS00001871B-page 31