LAN8820 Datasheet, PDF (26/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

LAN8820/LAN8820I
3.8.1.2.2
Configuring the Mode of Operation (CONFIG[3:2])
This section describes the initial modes of operation that are available using the CONFIG[3:2] configuration pins. The
user may configure additional modes using Software Configuration when the CONFIG[3:2] options do not include the
desired mode.
The CONFIG3 pin is used to configure the values of the MOD field (19.15:11) The configuration pin values for CONFIG3
and CONFIG2 should be selected using Table 3-8. These tables also detail how the MOD field of the Extended Mode
Control/Status Register will be configured.
Section 3.8.1.2.3 describes how the MOD field controls other configuration bits in the device. When a soft reset is issued
via the PHY Soft Reset (RESET) bit of the Basic Control Register, configuration is controlled by the register bit values
and the CONFIG[3:0] pins have no affect. Likewise, changing the MOD field of the Extended Mode Control/Status Reg-
ister bits does not change the configuration of the device in this case.
Note: Table 3-8 utilizes register index and bit number referencing in lieu of individual names.
TABLE 3-8: CONFIGURING THE MODE OF OPERATION
Mode Definitions
All mode capable (10/100/1000). Auto-negotiation enabled.
Auto master/slave resolution single port.
All mode capable (10/100/1000). Auto-negotiation enabled.
Auto master/slave resolution multi-port.
All mode capable (10/100/1000). Auto-negotiation enabled.
Manual master/slave resolution slave port.
All mode capable (10/100/1000). Auto-negotiation enabled.
Manual master/slave resolution master port.
CONFIG3
CPV(2)
CONFIG2
CPV(0)
CPV(2)
CPV(1)
CPV(2)
CPV(2)
CPV(2)
CPV(3)
Reg 19
[15:11]
10111
11000
11001
11010
3.8.1.2.3
Configuration Bits Impacted by the Mode of Operation
Immediately after a reset, the MOD field of the Extended Mode Control/Status Register will be set dependent on the
configuration pin values of the CONFIG3 and CONFIG2 pins, as described in Section 3.8.1.2.2. Table 3-9 details how
the MOD field effects other device configuration register bits.
Note: Table 3-9 utilizes register index and bit number referencing in lieu of individual names
DS00001871B-page 26
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