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| LAN8820 Datasheet, PDF (72/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver | |||
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LAN8820/LAN8820I
5.5.5.4 PHY RXC Delay Disabled Timing
FIGURE 5-8:
RGMII PHY RXC DELAY DISABLED TIMING
RXC
RXD[3:0]
RXCTRL
trxc
tclkh tclkl
tskew
RXD
[3:0]
RXD
[7:4]
tskew
RXDV
RXER
tskew
tskew
TABLE 5-17: RGMII PHY RXC DELAY DISABLED TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
trxc
tclkh
tclkl
tskew
RXC period
RXC high time
RXC low time
Data to clock output skew
Note 5-16 Note 5-17 Note 5-18
ns
Note 5-19
50
Note 5-20
%
Note 5-19
50
Note 5-20
%
-500
500
ps
Note 5-16
Note 5-17
Note 5-18
Note 5-19
Note 5-20
7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.
Minimum limits are non-sustainable long term.
8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.
Maximum limits are non-sustainable long term.
45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.
55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.
DS00001871B-page 72
ï£ 2009-2015 Microchip Technology Inc.
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