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| LAN8820 Datasheet, PDF (70/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver | |||
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LAN8820/LAN8820I
5.5.5.2 PHY TXC Delay Disabled Timing
FIGURE 5-6:
RGMII PHY TXC DELAY DISABLED TIMING
TXC
TXD[3:0]
TXCTRL
ttxc
tclkh tclkl
tsetup
thold
TXD
[3:0]
TXD
[7:4]
tsetup
thold
TXEN
TXER
tsetup
tsetup
thold
thold
TABLE 5-15: RGMII PHY TXC DELAY DISABLED TIMING VALUES
Symbol
ttxc
tclkh
tclkl
tsetup
thold
Description
TXC period
TXC high time
TXC low time
TXD[3:0], TXCTRL setup time to edge of TXC
TXD[3:0], TXCTRL hold time after edge of TXC
Min
Note 5-6
Note 5-9
Note 5-9
1.0
0.8
Typ
Note 5-7
50
50
Max
Note 5-8
Note 5-10
Note 5-10
Units
ns
%
%
ns
ns
Note 5-6
Note 5-7
Note 5-8
Note 5-9
Note 5-10
7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.
Minimum limits are non-sustainable long term.
8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.
Maximum limits are non-sustainable long term.
45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.
55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.
DS00001871B-page 70
ï£ 2009-2015 Microchip Technology Inc.
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