LAN8820 Datasheet, PDF (58/83 Pages) Microchip Technology – RGMII 10/100/1000 Ethernet Transceiver

LAN8820/LAN8820I
4.3.10 RECEIVE ERROR DURING DATA COUNTER REGISTER
Index:
U8
Size:
16 bits
Bits
Description
15:0 RXERIND_DATA[15:0]
Counts the assertions of RXER (going from low to high) when RXDV is high.
Note: The RXER and RXDV signals are extrapolated from the RXCTRL
pin.
Type
RO/
RC
Default
0000h
4.3.11 RECEIVE ERROR DURING IDLE COUNTER REGISTER
Index:
U9
Size:
16 bits
Bits
Description
15:0 RXERIND_IDLE[15:0]
Counts the assertions of RXER (going from low to high) when RXDV is low.
Note: The RXER and RXDV signals are extrapolated from the RXCTRL
pin.
Type
RO/
RC
Default
0000h
4.3.12 TRANSMIT PACKET COUNTER HIGH REGISTER
Index:
U10
Size:
16 bits
Bits
Description
15:0 TXPKT[47:32]
Counts the number of transmitted packets.
Contains the 16 upper bits of the 48-bit counter.
Reading this register resets all bits in the Transmit Packet Counter.
Type
RO/
RC
Default
0000h
Note:
The 48-bit transmit packet counter is split across 3 registers. In order to read the counter correctly, the reg-
isters must be read in the following order: Transmit Packet Counter Low Register, Transmit Packet Counter
Mid Register, Transmit Packet Counter High Register. After reading the high register, the counter will be
automatically cleared.
DS00001871B-page 58
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