PIC18F25K20T-ISO Datasheet, PDF (80/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
Timer0 Register, High Byte
Timer0 Register, Low Byte
TMR0ON T08BIT
IDLEN
IRCF2
VDIRMAG
—
—
—
IPEN
SBOREN⁽¹⁾
T0CS
IRCF1
IRVST
—
—
TMR1H
TMR1L
Timer1 Register, High Byte
Timer1 Register, Low Bytes
T0SE
IRCF0
HLVDEN
—
RI
PSA
OSTS
HLVDL3
—
TO
T0PS2
IOFS
HLVDL2
—
PD
T0PS1
SCS1
HLVDL1
—
POR
0000 0000 60, 157
xxxx xxxx 60, 157
T0PS0 1111 1111 60, 155
SCS0 0011 qq00 29, 60
HLVDL0 0-00 0101 60, 293
SWDTEN --- ---0 60, 309
BOR
0q-1 11q0 51, 58,
118
xxxx xxxx 60, 165
xxxx xxxx 60, 165
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 60, 159
Timer2 Register
0000 0000 60, 168
Timer2 Period Register
1111 1111 60, 168
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 60, 167
SSP Receive Buffer/Transmit Register
SSP Address Register in I²C™ Slave Mode. SSP Baud Rate Reload Register in I²C Master Mode.
xxxx xxxx 60, 201,
202
0000 0000 60, 202
SSPSTAT
SMP
CKE
D/A
SSPCON1
WCOL
SSPOV
SSPEN
SSPCON2
ADRESH
ADRESL
GCEN ACKSTAT ACKDT
A/D Result Register, High Byte
A/D Result Register, Low Byte
P
CKP
ACKEN
S
SSPM3
RCEN
R/W
SSPM2
PEN
UA
SSPM1
RSEN
BF
SSPM0
SEN
0000 0000 60, 194,
204
0000 0000 60, 195,
205
0000 0000 60, 206
xxxx xxxx 61, 277
xxxx xxxx 61, 277
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
PSTRCON
BAUDCON
PWM1CON
ECCP1AS
CVRCON
CVRCON2
TMR3H
TMR3L
—
—
CHS3
CHS2
—
—
VCFG1
VCFG0
ADFM
—
ACQT2
ACQT1
Capture/Compare/PWM Register 1, High Byte
Capture/Compare/PWM Register 1, Low Byte
P1M1
P1M0
DC1B1
DC1B0
Capture/Compare/PWM Register 2, High Byte
Capture/Compare/PWM Register 2, Low Byte
—
—
DC2B1
DC2B0
—
—
—
STRSYNC
ABDOVF
RCIDL
DTRXP
CKTXP
PRSEN
PDC6
PDC5
PDC4
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
CVREN
CVROE
CVRR
CVRSS
FVREN
FVRST
—
—
Timer3 Register, High Byte
Timer3 Register, Low Byte
CHS1
—
ACQT0
CCP1M3
CCP2M3
STRD
BRG16
PDC3
PSSAC1
CVR3
—
CHS0
—
ADCS2
CCP1M2
CCP2M2
STRC
—
PDC2
PSSAC0
CVR2
—
GO/DONE
—
ADCS1
CCP1M1
CCP2M1
STRB
WUE
PDC1
PSSBD1
CVR1
—
ADON
—
ADCS0
CCP1M0
CCP2M0
STRA
ABDEN
PDC0
PSSBD0
CVR0
—
--00 0000
--00 ----
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
---0 0001
0100 0-00
0000 0000
0000 0000
0000 0000
00-- ----
xxxx xxxx
xxxx xxxx
61, 271
59, 272
61, 273
61, 144
61, 144
61, 173
61, 144
61, 144
61, 143
61, 187
61, 248
61, 186
61, 183
61, 291
61, 292
61, 172
61, 172
T3CON
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 61, 169
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.
DS41303G-page 80
 2010 Microchip Technology Inc.