PIC18F25K20T-ISO Datasheet, PDF (143/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
11.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F2XK20/4XK20 devices have two CCP
Capture/Compare/PWM) modules. Each module
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
CCP1 is implemented as an enhanced CCP module with
standard Capture and Compare modes and enhanced
PWM modes. The ECCP implementation is discussed in
Section 16.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”. CCP2 is implemented as a standard
CCP module without the enhanced features.
The Capture and Compare operations described in this
chapter apply to both standard and enhanced CCP
modules.
Note: Throughout this section and Section 16.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to
generically by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the
module control register, regardless of whether
the CCP module is a standard or enhanced
implementation.
REGISTER 11-1: CCP2CON: STANDARD CAPTURE/COMPARE/PWM CONTROL REGISTER
U-0
—
bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1 CCP2M0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
DC2B<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP2 Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC2B<9:2>) of the duty cycle are found in CCPR2L.
CCP2M<3:0>: CCP2 Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP2 module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCP2IF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCP2 pin low; on compare match, force CCP2 pin high
(CCP2IF bit is set)
1001 = Compare mode: initialize CCP2 pin high; on compare match, force CCP2 pin low
(CCP2IF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCP2IF bit is set,
CCP2 pin reflects I/O state)
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
CCP2 match (CCP2IF bit is set)
11xx = PWM mode
 2010 Microchip Technology Inc.
DS41303G-page 143