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PIC18F25K20T-ISO Datasheet, PDF (337/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology | |||
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PIC18F2XK20/4XK20
INCFSZ
Increment f, skip if 0
Syntax:
INCFSZ f {,d {,a}}
Operands:
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
Operation:
(f) + 1 ï® dest,
skip if result = 0
Status Affected:
None
Encoding:
0011 11da ffff ffff
Description:
The contents of register âfâ are
incremented. If âdâ is â0â, the result is
placed in W. If âdâ is â1â, the result is
placed back in register âfâ (default).
If the result is â0â, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank.
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See
Section 24.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
If skip:
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Before Instruction
PC
=
After Instruction
CNT =
If CNT =
PC
=
If CNT ï¹
PC
=
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
INFSNZ
Increment f, skip if not 0
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
INFSNZ f {,d {,a}}
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
(f) + 1 ï® dest,
skip if result ï¹ 0
None
0100 10da ffff ffff
The contents of register âfâ are
incremented. If âdâ is â0â, the result is
placed in W. If âdâ is â1â, the result is
placed back in register âfâ (default).
If the result is not â0â, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank.
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See
Section 24.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register âfâ
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
=
After Instruction
REG =
If REG ï¹
PC
=
If REG =
PC
=
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
ï£ 2010 Microchip Technology Inc.
DS41303G-page 337
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