PIC18F25K20T-ISO Datasheet, PDF (124/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., disable the output driver). Clearing a
TRISB bit (= 0) will make the corresponding PORTB
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 10-2: INITIALIZING PORTB
CLRF
CLRF
CLRF
MOVLW
MOVWF
PORTB
LATB
ANSELH
0CFh
TRISB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Set RB<4:0> as
; digital I/O pins
;(required if config bit
; PBADEN is set)
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
10.3 Additional PORTB Pin Functions
PORTB pins RB<7:4> have an interrupt-on-change
option. All PORTB pins have a weak pull-up option. An
alternate CCP2 peripheral option is available on RB3.
10.3.1 WEAK PULL-UPS
Each of the PORTB pins has an individually controlled
weak internal pull-up. When set, each bit of the WPUB
register enables the corresponding pin pull-up. When
cleared, the RBPU bit of the INTCON2 register enables
pull-ups on all pins which also have their corresponding
WPUB bit set. When set, the RBPU bit disables all
weak pull-ups. The weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset.
Note:
On a Power-on Reset, RB<4:0> are
configured as analog inputs by default and
read as ‘0’; RB<7:5> are configured as
digital inputs.
When the PBADEN Configuration bit is set
to ‘1’, RB<4:0> will alternatively be
configured as digital inputs on POR.
10.3.2 INTERRUPT-ON-CHANGE
Four of the PORTB pins (RB<7:4>) are individually
configurable as interrupt-on-change pins. Control bits
in the IOCB register enable (when set) or disable (when
clear) the interrupt function for each pin.
When set, the RBIE bit of the INTCON register enables
interrupts on all pins which also have their correspond-
ing IOCB bit set. When clear, the RBIE bit disables all
interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any RB<7:4> pin configured as an output
is excluded from the interrupt-on-change comparison).
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Interrupt flag
bit (RBIF) in the INTCON register.
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a) Any read or write of PORTB to clear the mis-
match condition (except when PORTB is the
source or destination of a MOVFF instruction).
b) Clear the flag bit, RBIF.
A mismatch condition will continue to set the RBIF flag bit.
Reading or writing PORTB will end the mismatch
condition and allow the RBIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After either one of these Resets, the
RBIF flag will continue to be set if a mismatch is present.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all bits
of that port, care must be taken when using
multiple pins in Interrupt-on-change mode.
Changes on one pin may not be seen while
servicing changes on another pin.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
10.3.3 ALTERNATE CCP2 OPTION
RB3 can be configured as the alternate peripheral pin
for the CCP2 module by clearing the CCP2MX Config-
uration bit of CONFIG3H. The default state of the
CCP2MX Configuration bit is ‘1’ which selects RC1 as
the CCP2 peripheral pin.
DS41303G-page 124
 2010 Microchip Technology Inc.