PIC18F25K20T-ISO Datasheet, PDF (300/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F2XK20/4XK20
23.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs
File Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
300001h CONFIG1H IESO FCMEN —
—
FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111
300002h CONFIG2L —
—
—
BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
300003h CONFIG2H —
—
— WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE —
—
—
HFOFST LPT1OSC PBADEN CCP2MX 1--- 1011
300006h CONFIG4L DEBUG XINST
—
300008h CONFIG5L —
—
—
—
—
LVP
—
STVREN 10-- -1-1
—
CP3⁽¹⁾
CP2⁽¹⁾
CP1
CP0
---- 1111
300009h CONFIG5H CPD
CPB
—
30000Ah CONFIG6L —
—
—
—
—
—
—
—
11-- ----
—
WRT3⁽¹⁾ WRT2⁽¹⁾ WRT1
WRT0
---- 1111
30000Bh CONFIG6H WRTD WRTB WRTC
30000Ch CONFIG7L —
—
—
—
—
—
—
—
111- ----
—
EBTR3⁽¹⁾ EBTR2⁽¹⁾ EBTR1 EBTR0 ---- 1111
30000Dh
3FFFFEh
3FFFFFh
CONFIG7H
DEVID1⁽²⁾
DEVID2⁽²⁾
—
DEV2
DEV10
EBTRB
DEV1
DEV9
—
DEV0
DEV8
—
REV4
DEV7
—
REV3
DEV6
—
REV2
DEV5
—
REV1
DEV4
—
REV0
DEV3
-1-- ----
qqqq qqqq⁽²⁾
0000 1100
Legend:
Note 1:
2:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
Implemented but not used in PIC18FX3K20 and PIC18FX4K20 devices; maintain this bit set.
See Register 23-12 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
DS41303G-page 300
 2010 Microchip Technology Inc.