PIC18F25K20T-ISO Datasheet, PDF (133/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

10.6 PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F2XK20/4XK20
device selected, PORTE is implemented in two
different ways.
10.6.1 PORTE IN PIC18F4XK20 DEVICES
For PIC18F4XK20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/
AN7) are individually configurable as inputs or outputs.
These pins have Schmitt Trigger input buffers. When
selected as an analog input, these pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., disable the output driver).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note: On a Power-on Reset, RE<2:0> are
configured as analog inputs.
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
PIC18F2XK20/4XK20
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE
Configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with its
operation. Otherwise, it functions as the device’s Master
Clear input. In either configuration, RE3 also functions as
the programming voltage input during programming.
Note:
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
EXAMPLE 10-5: INITIALIZING PORTE
CLRF
CLRF
MOVLW
ANDWF
MOVLW
MOVWF
PORTE ; Initialize PORTE by
; clearing output
; data latches
LATE ; Alternate method
; to clear output
; data latches
1Fh
; Configure analog pins
ANSEL,w ; for digital only
05h
; Value used to
; initialize data
; direction
TRISE ; Set RE<0> as input
; RE<1> as output
; RE<2> as input
10.6.2 PORTE IN PIC18F2XK20 DEVICES
For PIC18F2XK20 devices, PORTE is only available
when Master Clear functionality is disabled
(MCLR = 0). In these cases, PORTE is a single bit,
input only port comprised of RE3 only. The pin operates
as previously described.
 2010 Microchip Technology Inc.
DS41303G-page 133