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PIC18F25K20T-ISO Datasheet, PDF (310/456 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
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PIC18F2XK20/4XK20
23.3 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® microcontroller devices.
The user program memory is divided into three or five
blocks, depending on the device. One of these is a
Boot Block of 0.5K or 2K bytes, depending on the
device. The remainder of the memory is divided into
individual blocks on binary boundaries.
Each of the blocks has three code protection bits asso-
ciated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-2 shows the program memory organization
for 8, 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
FIGURE 23-2:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2XK20/4XK20
8 Kbytes
(PIC18FX3K20)
MEMORY SIZE/DEVICE
16 Kbytes
(PIC18FX4K20)
32 Kbytes
(PIC18FX5K20)
64 Kbytes
(PIC18FX6K20)
Block Code Protection
Controlled By:
Boot Block
(000h-1FFh)
Block 0
(200h-FFFh)
Block 1
(1000h-1FFFh)
Boot Block
(000h-7FFh)
Block 0
(800h-1FFFh)
Block 1
(2000h-3FFFh)
Boot Block
(000h-7FFh)
Block 0
(800h-1FFFh)
Block 1
(2000h-3FFFh)
Block 2
(4000h-5FFFh)
Block 3
(6000h-7FFFh)
Boot Block
(000h-7FFh)
Block 0
(800h-3FFFh)
Block 1
(4000h-7FFFh)
Block 2
(8000h-BFFFh)
Block 3
(C000h-FFFFh)
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
(2000h-1FFFFFh)
Unimplemented
Read ‘0’s
(4000h-1FFFFFh)
Unimplemented Unimplemented
Read ‘0’s
Read ‘0’s
(8000h-1FFFFFh) (10000h-1FFFFFh)
(Unimplemented
Memory Space)
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
300008h CONFIG5L —
—
—
—
CP3(1)
CP2(1)
300009h CONFIG5H CPD
CPB
—
30000Ah CONFIG6L —
—
—
—
—
—
—
WRT3(1) WRT2(1)
30000Bh CONFIG6H WRTD
30000Ch CONFIG7L —
WRTB
—
WRTC
—
—
—
—
—
EBTR3(1) EBTR2(1)
30000Dh CONFIG7H — EBTRB
—
—
—
—
Legend: Shaded cells are unimplemented.
Note 1: Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices.
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
DS41303G-page 310
 2010 Microchip Technology Inc.
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