PIC18F2X1X Datasheet, PDF(69/380 Page) Microchip Technology – 28/40/44-PIN FLASH MICROCONTROLLERS WITH 10-BIT A/D AND NANO WATT TECHNOLOGY

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

PIC18F2X1X Datasheet, PDF (69/380 Pages) Microchip Technology – 28/40/44-PIN FLASH MICROCONTROLLERS WITH 10-BIT A/D AND NANO WATT TECHNOLOGY

◁

PIC18F2X1X/4X1X

TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2X1X/4X1X) (CONTINUED)

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on Details

POR, BOR on page:

SPBRGH

SPBRG

RCREG

TXREG

TXSTA

RCSTA

IPR2

PIR2

PIE2

IPR1

PIR1

PIE1

OSCTUNE

TRISE(2)

TRISD(2)

TRISC

TRISB

TRISA

LATE(2)

LATD(2)

LATC

LATB

LATA

PORTE

PORTD(2)

PORTC

PORTB

PORTA

Legend:

Note 1:

2:

3:

4:

5:

6:

EUSART Baud Rate Generator Register High Byte

0000 0000 51, 195

EUSART Baud Rate Generator Register Low Byte

0000 0000 51, 195

EUSART Receive Register

0000 0000 51, 202

EUSART Transmit Register

0000 0000 51, 200

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D 0000 0010 51, 192

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D 0000 000x 51, 193

OSCFIP

CMIP

â

â

BCLIP

HLVDIP

TMR3IP

CCP2IP 11-- 1111 52, 91

OSCFIF

CMIF

â

â

BCLIF

HLVDIF

TMR3IF

CCP2IF 00-- 0000 52, 87

OSCFIE

PSPIP(2)

PSPIF(2)

PSPIE(2)

INTSRC

CMIE

ADIP

ADIF

ADIE

PLLEN(3)

â

RCIP

RCIF

RCIE

â

â

TXIP

TXIF

TXIE

TUN4

BCLIE

SSPIP

SSPIF

SSPIE

TUN3

HLVDIE

CCP1IP

CCP1IF

CCP1IE

TUN2

TMR3IE

TMR2IP

TMR2IF

TMR2IE

TUN1

CCP2IE

TMR1IP

TMR1IF

TMR1IE

TUN0

00-- 0000

1111 1111

0000 0000

0000 0000

0q-0 0000

52, 89

52, 90

52, 86

52, 88

27, 52

IBF

OBF

IBOV PSPMODE

â

TRISE2

TRISE1

TRISE0 0000 -111 52, 108

PORTD Data Direction Control Register

1111 1111 52, 104

PORTC Data Direction Control Register

1111 1111 52, 101

PORTB Data Direction Control Register

TRISA7(5) TRISA6(5) Data Direction Control Register for PORTA

1111 1111 52, 98

1111 1111 52, 95

â

â

â

â

â

PORTE Data Latch Register

---- -xxx 52, 107

(Read and Write to Data Latch)

PORTD Data Latch Register (Read and Write to Data Latch)

xxxx xxxx 52, 104

PORTC Data Latch Register (Read and Write to Data Latch)

xxxx xxxx 52, 101

PORTB Data Latch Register (Read and Write to Data Latch)

LATA7(6) LATA6(6) PORTA Data Latch Register (Read and Write to Data Latch)

â

â

â

â

RE3(4)

RE2(2)

RE1(2)

RE0(2)

xxxx xxxx

xxxx xxxx

---- xxxx

52, 98

52, 95

52, 107

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0 xxxx xxxx 52, 104

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0 xxxx xxxx 52, 101

RB7

RA7(5)

RB6

RA6(5)

RB5

RA5

RB4

RA4

RB3

RA3

RB2

RA2

RB1

RA1

RB0 xxxx xxxx 52, 98

RA0 xx0x 0000 52, 95

x = unknown, u = unchanged, â = unimplemented, q = value depends on condition

The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, it is disabled and reads as â0â. See

Section 4.4 âBrown-out Reset (BOR)â.

These registers and/or bits are not implemented on 28-pin devices and are read as â0â. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as â-â.

The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as â0â. See Section 2.6.4 âPLL in

INTOSC Modesâ.

The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as â0â. This bit is

read-only.

RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

When disabled, these bits read as â0â.

Bit 7 and bit 6 are cleared by user software or by a POR.

ï£© 2004 Microchip Technology Inc.

Preliminary

DS39636A-page 67

▷