PIC18F2X1X Datasheet, PDF (104/380 Pages) Microchip Technology – 28/40/44-PIN FLASH MICROCONTROLLERS WITH 10-BIT A/D AND NANO WATT TECHNOLOGY

PIC18F2X1X/4X1X
TABLE 9-5: PORTC I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RC0/T1OSO/
T13CKI
RC0
0
O
DIG LATC<0> data output.
1
I
ST PORTC<0> data input.
T1OSO
x
O
ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T13CKI
1
I
ST Timer1/Timer3 counter input.
RC1/T1OSI/CCP2 RC1
0
O
DIG LATC<1> data output.
1
I
ST PORTC<1> data input.
T1OSI
x
CCP2⁽¹⁾
0
I
ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
O
DIG CCP2 compare and PWM output; takes priority over port data.
1
I
ST CCP2 capture input.
RC2/CCP1/P1A
RC2
0
O
DIG LATC<2> data output.
1
I
ST PORTC<2> data input.
CCP1
0
O
DIG ECCP1 compare or PWM output; takes priority over port data.
1
P1A⁽²⁾
0
I
ST ECCP1 capture input.
O
DIG ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RC3/SCK/SCL
RC3
0
O
DIG LATC<3> data output.
1
I
ST PORTC<3> data input.
SCK
0
O
DIG SPI clock output (MSSP module); takes priority over port data.
1
I
ST SPI clock input (MSSP module).
SCL
0
O
DIG I²C™ clock output (MSSP module); takes priority over port data.
1
I I²C/SMB I²C clock input (MSSP module); input type depends on module setting.
RC4/SDI/SDA
RC4
0
O
DIG LATC<4> data output.
1
I
ST PORTC<4> data input.
SDI
SDA
1
I
ST SPI™ data input (MSSP module).
1
O
DIG I²C data output (MSSP module); takes priority over port data.
1
I I²C/SMB I²C data input (MSSP module); input type depends on module setting.
RC5/SDO
RC5
0
O
DIG LATC<5> data output.
1
I
ST PORTC<5> data input.
SDO
0
O
DIG SPI data output (MSSP module); takes priority over port data.
RC6/TX/CK
RC6
0
O
DIG LATC<6> data output.
1
I
ST PORTC<6> data input.
TX
1
O
DIG Asynchronous serial transmit data output (USART module);
takes priority over port data. User must configure as output.
CK
1
O
DIG Synchronous serial clock output (USART module); takes priority
over port data.
1
I
ST Synchronous serial clock input (USART module).
RC7/RX/DT
RC7
0
O
DIG LATC<7> data output.
1
I
ST PORTC<7> data input.
RX
1
I
ST Asynchronous serial receive data input (USART module).
DT
1
O
DIG Synchronous serial data output (USART module); takes priority over
port data.
1
I
ST Synchronous serial data input (USART module). User must
configure as an input.
Legend:
Note 1:
2:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I²C/SMB = I²C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3.
Enhanced PWM output is available only on PIC18F4410/4510/4515/4610 devices.
DS39636A-page 102
Preliminary
 2004 Microchip Technology Inc.