PIC18F2X1X Datasheet, PDF (262/380 Pages) Microchip Technology – 28/40/44-PIN FLASH MICROCONTROLLERS WITH 10-BIT A/D AND NANO WATT TECHNOLOGY

PIC18F2X1X/4X1X
TABLE 23-2: PIC18FXXXX INSTRUCTION SET
Mnemonic,
Operands
Description
16-Bit Instruction Word
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f_s, f_d
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move f_s (source) to 1st word
f_d (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
1
0010
1
0010
1
0001
1
0110
1
0001
1 (2 or 3) 0110
1 (2 or 3) 0110
1 (2 or 3) 0110
1
0000
1 (2 or 3) 0010
1 (2 or 3) 0100
1
0010
1 (2 or 3) 0011
1 (2 or 3) 0100
1
0001
1
0101
2
1100
1111
1
0110
1
0000
1
0110
1
0011
1
0100
1
0011
1
0100
1
0110
1
0101
1
0101
1
0101
1
0011
1 (2 or 3) 0110
1
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff C, DC, Z, OV, N 1, 2
ffff C, DC, Z, OV, N 1, 2
ffff Z, N
1,2
ffff Z
2
ffff Z, N
1, 2
ffff None
4
ffff None
4
ffff None
1, 2
ffff C, DC, Z, OV, N 1, 2, 3, 4
ffff None
1, 2, 3, 4
ffff None
1, 2
ffff C, DC, Z, OV, N 1, 2, 3, 4
ffff None
4
ffff None
1, 2
ffff Z, N
1, 2
ffff Z, N
1
ffff None
ffff
ffff None
ffff None
1, 2
ffff C, DC, Z, OV, N
ffff C, Z, N
1, 2
ffff Z, N
ffff C, Z, N
ffff Z, N
ffff None
1, 2
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N 1, 2
ffff C, DC, Z, OV, N
ffff None
4
ffff None
1, 2
ffff Z, N
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
DS39636A-page 260
Preliminary
 2004 Microchip Technology Inc.