PIC18F2X1X Datasheet, PDF (375/380 Pages) Microchip Technology – 28/40/44-PIN FLASH MICROCONTROLLERS WITH 10-BIT A/D AND NANO WATT TECHNOLOGY

CLKO and I/O .......................................................... 335
Clock Synchronization ............................................. 171
Clock/Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 340
Example SPI Master Mode (CKE = 1) ..................... 341
Example SPI Slave Mode (CKE = 0) ....................... 342
Example SPI Slave Mode (CKE = 1) ....................... 343
External Clock (All Modes except PLL) .................... 333
Fail-Safe Clock Monitor ............................................ 250
First Start Bit Timing ................................................ 179
Full-Bridge PWM Output .......................................... 143
Half-Bridge PWM Output ......................................... 142
High/Low-Voltage Detect Characteristics ................ 330
High-Voltage Detect (VDIRMAG = 1) ...................... 234
I²C Bus Data ............................................................ 344
I²C Bus Start/Stop Bits ............................................. 344
I²C Master Mode (7 or
10-Bit Transmission) ........................................ 182
I²C Master Mode (7-Bit Reception) .......................... 183
I²C Slave Mode (10-Bit Reception,
SEN = 0) .......................................................... 168
I²C Slave Mode (10-Bit Reception,
SEN = 1) .......................................................... 173
I²C Slave Mode (10-Bit Transmission) ..................... 169
I²C Slave Mode (7-Bit Reception,
SEN = 0) .......................................................... 166
I²C Slave Mode (7-Bit Reception,
SEN = 1) .......................................................... 172
I²C Slave Mode (7-Bit Transmission) ....................... 167
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 174
I²C Stop Condition Receive or
Transmit Mode ................................................. 184
Low-Voltage Detect (VDIRMAG = 0) ....................... 233
Master SSP I²C Bus Data ........................................ 346
Master SSP I²C Bus Start/Stop Bits ........................ 346
Parallel Slave Port
(PIC18F4410/4510/4515/4610) ....................... 339
Parallel Slave Port (PSP) Read ............................... 111
Parallel Slave Port (PSP) Write ............................... 111
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 148
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 148
PWM Direction Change ........................................... 145
PWM Direction Change at Near
100% Duty Cycle ............................................. 145
PWM Output ............................................................ 134
Repeat Start Condition ............................................. 180
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 336
Send Break Character Sequence ............................ 205
Slave Synchronization ............................................. 157
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
SPI Mode (Master Mode) ......................................... 156
SPI Mode (Slave Mode, CKE = 0) ........................... 158
SPI Mode (Slave Mode, CKE = 1) ........................... 158
Synchronous Reception
(Master Mode, SREN) ..................................... 208
PIC18F2X1X/4X1X
Synchronous Transmission ..................................... 206
Synchronous Transmission
(Through TXEN) .............................................. 207
Time-out Sequence on POR w/PLL
Enabled (MCLR Tied to VDD) ............................ 47
Time-out Sequence on Power-up
(MCLR Not Tied to VDD, Case 1) ...................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD, Case 2) ...................... 46
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 46
Timer0 and Timer1 External Clock .......................... 337
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 248
Transition for Wake from Idle to
Run Mode .......................................................... 38
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 36
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 35
Transition to RC_RUN Mode ..................................... 36
USART Synchronous Receive
(Master/Slave) ................................................. 348
USART Synchronous Transmission
(Master/Slave) ................................................. 348
Timing Diagrams and Specifications ............................... 333
A/D Conversion Requirements ................................ 350
Capture/Compare/PWM (CCP)
Requirements .................................................. 338
CLKO and I/O Requirements ................................... 335
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 340
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 341
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 342
Example SPI Mode Requirements
(Slave Mode, CKE = 1) .................................... 343
External Clock Requirements .................................. 333
I²C Bus Data Requirements
(Slave Mode) ................................................... 345
Master SSP I²C Bus Data Requirements ................ 347
Master SSP I²C Bus Start/Stop Bits
Requirements .................................................. 346
Parallel Slave Port Requirements
(PIC18F4410/4510/4515/4610) ....................... 339
PLL Clock ................................................................ 334
Reset, Watchdog Timer,
Oscillator Start-up Timer,
Power-up Timer and
Brown-out Reset Requirements ...................... 336
Timer0 and Timer1 External
Clock Requirements ........................................ 337
USART Synchronous
Receive Requirements .................................... 348
USART Synchronous
Transmission Requirements ............................ 348
 2004 Microchip Technology Inc.
Preliminary
DS39636A-page 373