PIC18F2X1X Datasheet, PDF (141/380 Pages) Microchip Technology – 28/40/44-PIN FLASH MICROCONTROLLERS WITH 10-BIT A/D AND NANO WATT TECHNOLOGY

15.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the P1M1:P1M0 and
CCP1M3:CCP1M0 bits of the CCP1CON register.
Figure 15-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Delay register, PWM1CON, which is loaded
at either the duty cycle boundary or the period bound-
ary (whichever comes first). Because of the buffering,
the module waits until the assigned timer resets instead
of starting immediately. This means that Enhanced
PWM waveforms do not exactly match the standard
PWM waveforms, but are instead offset by one full
instruction cycle (4 TOSC).
As before, the user must manually configure the
appropriate TRIS bits for output.
PIC18F2X1X/4X1X
15.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 15-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
Note:
The Timer2 postscaler (see Section 12.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
FIGURE 15-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
Duty Cycle Registers
CCPR1L
CCP1CON<5:4>
CCPR1H (Slave)
Comparator
R
TMR2
(Note 1)
S
Comparator
PR2
Clear Timer,
set CCP1 pin and
latch D.C.
P1M1<1:0>
2
CCP1M<3:0>
4
CCP1/P1A
TRISx<x>
P1B
Q
Output
Controller
TRISx<x>
P1C
TRISx<x>
P1D
PWM1CON
TRISx<x>
CCP1/P1A
P1B
P1C
P1D
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time
base.
 2004 Microchip Technology Inc.
Preliminary
DS39636A-page 139