PIC16F872 Datasheet, PDF (63/160 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller

PIC16F872
9.2.1.2 SLAVE RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
Note:
The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSP-
BUF is updated.
TABLE 9-2 DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
BF
SSPOV
SSPSR → SSPBUF
Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
1
No
No
Yes
0
1
Yes
No
Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
9.2.1.3 SLAVE TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP (SSP-
CON<4>). The master must monitor the SCL pin prior
to asserting another clock pulse. The slave devices
may be holding off the master by stretching the clock.
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 9-7).
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (not ACK), then the
data transfer is complete. When the not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin should be enabled
by setting the CKP bit.
FIGURE 9-6: I²C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
Receiving Address
R/W=0
ACK
Receiving Data
ACK
Receiving Data
Not
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL S 1 2 ³ 4 5 ^{6 7} 8 ^{9 1 2 3 4 5 6 7 8 9 1 2 3} 4 ^{5 6 7 8 9}
P
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
Cleared in software
SSPBUF register is read
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
Bus Master
terminates
transfer
© 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 63