PIC16F872 Datasheet, PDF (140/160 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller

PIC16F872
FIGURE 14-15: I²C BUS DATA TIMING
103
100
101
SCL
SDA
In
90
91
106
107
109
109
SDA
Out
Note: Refer to Figure 14-3 for load conditions.
102
92
110
TABLE 14-8: I²C BUS DATA REQUIREMENTS
Param
No.
Sym Characteristic
Min
Max Units
Conditions
100
THIGH Clock high time
100 kHz mode
4.0
—
µs Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
0.6
—
µs Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
101
TLOW Clock low time
100 kHz mode
4.7
—
µs Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
1.3
—
µs Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
102
TR
SDA and SCL rise
100 kHz mode
—
1000 ns
time
400 kHz mode 20 + 0.1Cb 300
ns Cb is specified to be from
10 to 400 pF
103
TF
SDA and SCL fall time 100 kHz mode
—
300
ns
400 kHz mode 20 + 0.1Cb 300
ns Cb is specified to be from
10 to 400 pF
90
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
91
THD:STA START condition hold 100 kHz mode
time
400 kHz mode
106
THD:DAT Data input hold time 100 kHz mode
400 kHz mode
4.7
—
µs Only relevant for repeated
0.6
—
µs ^{START condition}
4.0
—
µs After this period the first clock
0.6
—
µs ^{pulse is generated}
0
—
ns
0
0.9
µs
107
TSU:DAT Data input setup time 100 kHz mode
250
—
ns Note 2
400 kHz mode
100
—
ns
92
TSU:STO STOP condition setup 100 kHz mode
time
400 kHz mode
4.7
—
µs
0.6
—
µs
109
TAA Output valid from
100 kHz mode
clock
400 kHz mode
—
3500 ns Note 1
—
—
ns
110
TBUF Bus free time
100 kHz mode
400 kHz mode
4.7
—
µs Time the bus must be free
1.3
—
µs ^{before a new transmission can}
start
Cb Bus capacitive loading
—
400 pF
Note 1:
2:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the requirement tsu;
DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before the SCL line is
released.
DS30221A-page 140
Preliminary
© 1999 Microchip Technology Inc.