PIC16F872 Datasheet, PDF(49/160 Page) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller

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PIC16F872 Datasheet, PDF (49/160 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller

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8.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

â¢ Driven high

â¢ Driven low

â¢ Remains unchanged

The action on the pin is based on the value of control

bits CCP1M<3:0> (CCP1CON<3:0>). At the same

time, interrupt flag bit CCP1IF is set.

FIGURE 8-2: COMPARE MODE OPERATION

BLOCK DIAGRAM

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>).

Special Event Trigger

Set flag bit CCP1IF

(PIR1<2>)

CCPR1H CCPR1L

RC2/CCP1

TRISC<2>

Output Enable

S Output

Logic

match

CCP1CON<3:0>

Mode Select

Comparator

TMR1H TMR1L

8.2.1 CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

8.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

8.2.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen, the

CCP1 pin is not affected. The CCPIF bit is set causing

a CCP interrupt (if enabled).

8.2.4 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair and starts an A/D conversion (if the

A/D module is enabled). This allows the CCPR1 regis-

ter to effectively be a 16-bit programmable period reg-

ister for Timer1.

PIC16F872

Note:

The special event trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

8.3 PWM Mode (PWM)

In pulse width modulation mode, the CCP1 pin pro-

duces up to a 10-bit resolution PWM output. Since the

CCP1 pin is multiplexed with the PORTC data latch, the

TRISC<2> bit must be cleared to make the CCP1 pin

an output.

Note:

Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

Figure 8-3 shows a simplified block diagram of the CCP

module in PWM mode.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 8.3.3.

FIGURE 8-3: SIMPLIFIED PWM BLOCK

DIAGRAM

Duty Cycle Registers

CCPR1L

CCP1CON<5:4>

CCPR1H (Slave)

Comparator

TMR2

(Note 1)

Comparator

PR2

Clear Timer,

CCP1 pin and

latch D.C.

RC2/CCP1

TRISC<2>

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

Preliminary

DS30221A-page 49

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