PIC16F872 Datasheet, PDF (42/160 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller

PIC16F872
6.1 Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
6.2 Timer1 Counter Operation
Timer1 may operate in asynchronous or usynchronous
mode depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in counter mode, the module must first have
a falling edge before the counter begins to increment.
T1CKI
(Default low)
Note: Arrows indicate counter increments.
6.3 Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI, when bit T1OSCEN is
set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN
is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
RC0/T1OSO/T1CKI
RC1/T1OSI⁽²⁾
TMR1
0
TMR1H
T1OSC
TMR1L
1
TMR1ON
on/off
T1SYNC
(2)
1
T1OSCEN _FOSC/4
Enable
Oscillator⁽¹⁾
Internal
Clock
0
Prescaler
1, 2, 4, 8
2
T1CKPS<1:0>
TMR1CS
Synchronized
clock input
Synchronize
det
Q Clock
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F872, the Schmitt Trigger is not implemented in external clock mode.
DS30221A-page 42
Preliminary
© 1999 Microchip Technology Inc.