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PIC16F872 Datasheet, PDF (11/160 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller
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PIC16F872
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
Bank 2
100h(3)
101h
102h(3)
103h(3)
104h(3)
105h
106h
107h
108h
109h
10Ah(1,3)
10Bh(3)
10Ch
10Dh
10Eh
10Fh
INDF
TMR0
PCL
STATUS
FSR
—
PORTB
—
—
—
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
EEPROM data register
EEPROM address register
—
—
EEPROM data register high byte
—
—
—
EEPROM address register high byte
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
—
—
xxxx xxxx uuuu uuuu
—
—
—
—
—
—
---0 0000 ---0 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Bank 3
180h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
182h(3)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
183h(3)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
184h(3)
FSR
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
185h
—
Unimplemented
—
—
186h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
18Ah(1,3) PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
18Bh(3) INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
18Ch
EECON1
EEPGD
—
—
—
WRERR WREN
WR
RD x--- x000 x--- u000
18Dh
EECON2
EEPROM control register2 (not a physical register)
---- ---- ---- ----
18Eh
—
Reserved maintain clear
0000 0000 0000 0000
18Fh
—
Reserved maintain clear
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: These bits are reserved; always maintain these bits clear.
© 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 11
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