PIC16F872 Datasheet, PDF (107/160 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller

PIC16F872
11.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
Note:
.
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 11-10: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
WDT Timer
0
1
M
U
X
Postscaler
8
WDT
Enable Bit
PSA
8 - to - 1 MUX
PS<2:0>
To TMR0 (Figure 5-1)
0
1
MUX
PSA
Note: PSA and PS<2:0> are bits in the OPTION_REG register.
WDT
Time-out
FIGURE 11-11: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name
Bit 7
Bit 6
Bit 5
2007h
Config. bits
(1)
BODEN⁽¹⁾
CP1
81h,181h OPTION_REG RBPU
INTEDG
T0CS
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.
Bit 4
CP0
T0SE
Bit 3
PWRTE⁽¹⁾
PSA
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
© 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 107