PIC16F872 Datasheet, PDF (10/160 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller

PIC16F872
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
Bank 1
80h⁽³⁾
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
82h⁽³⁾
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 0000 0000
83h⁽³⁾
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
84h⁽³⁾
FSR
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
85h
TRISA
—
—
PORTA Data Direction Register
--11 1111 --11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah^(1,3) PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
8Bh⁽³⁾
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
8Ch
PIE1
(4)
ADIE
(4)
(4)
SSPIE CCP1IE TMR2IE TMR1IE r0rr 0000 r0rr 0000
8Dh
PIE2
—
(4)
—
EEIE
BCLIE
—
—
(4)
-r-0 0--r -r-0 0--r
8Eh
PCON
—
—
—
—
—
—
POR
BOR ---- --qq ---- --uu
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
SSPCON2
GCEN ACKSTAT ACKDT ACKEN
RCEN
PEN
RSEN
SEN 0000 0000 0000 0000
92h
PR2
Timer2 Period Register
1111 1111 1111 1111
93h
SSPADD
Synchronous Serial Port (I²C mode) Address Register
0000 0000 0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
9Fh
ADCON1
ADFM
—
—
—
PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 0--- 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: These bits are reserved; always maintain these bits clear.
DS30221A-page 10
Preliminary
© 1999 Microchip Technology Inc.