PIC16F872 Datasheet, PDF (61/160 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontroller

9.2 MSSP I²C Operation
The MSSP module in I²C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts-on-start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Refer to Application Note AN578, "Use of the SSP
Module in the I ²C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
FIGURE 9-5: I²C SLAVE MODE BLOCK
DIAGRAM
Internal
Data Bus
Read
Write
SCL
SDA
SSPBUF reg
Shift
Clock
SSPSR reg
MSb
LSb
Match detect
Addr Match
SSPADD reg
Start and
Stop bit detect
Set, Reset
S, P bits
(SSPSTAT reg)
PIC16F872
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
ured when the I²C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>).
The MSSP module has six registers for I²C operation.
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I²C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I²C modes to be selected:
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I²C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I²C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I²C mode.
The CKE bit (SSPSTAT<6:7>) sets the levels of the
SDA and SCL pins in either Master or Slave mode.
When CKE = 1, the levels will conform to the SMBUS
specification. When CKE = 0, the levels will conform to
the I²C specification.
© 1999 Microchip Technology Inc.
Preliminary
DS30221A-page 61