70291E Datasheet, PDF (54/436 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

TABLE 4-15: SPI1 REGISTER MAP
SFR Name
SFR
Addr
Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
0240 SPIEN
—
SPISIDL —
—
—
—
—
— SPIROV
0242
—
—
— DISSCK DISSDO MODE16 SMP
CKE SSEN CKP
0244 FRMEN SPIFSD FRMPOL —
—
—
—
—
—
—
0248
SPI1 Transmit and Receive Buffer Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
MSTEN
—
Bit 4
Bit 3
Bit 2
—
—
—
SPRE<2:0>
—
—
—
Bit 1
Bit 0
All
Resets
SPITBF SPIRBF
PPRE<1:0>
FRMDLY —
0000
0000
0000
0000
TABLE 4-16: SPI2 REGISTER MAP
SFR Name
SFR
Addr
Bit 15
Bit 14
Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
SPI2STAT 0260 SPIEN
—
SPISIDL —
—
—
—
—
— SPIROV
SPI2CON1 0262
—
—
— DISSCK DISSDO MODE16 SMP
CKE SSEN CKP
SPI2CON2 0264 FRMEN SPIFSD FRMPOL —
—
—
—
—
—
—
SPI2BUF 0268
SPI2 Transmit and Receive Buffer Register
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
MSTEN
—
Bit 4
Bit 3
Bit 2
—
—
—
SPRE<2:0>
—
—
—
Bit 1
Bit 0
All
Resets
SPITBF SPIRBF
PPRE<1:0>
FRMDLY —
0000
0000
0000
0000
TABLE 4-17: ADC1 REGISTER MAP FOR dsPIC33FJ64MC202/802, dsPIC33FJ128MC202/802 AND dsPIC33FJ32MC302
File Name Addr Bit 15 Bit 14 Bit 13
Bit 12
Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADC1BUF0 0300
ADC Data Buffer 0
AD1CON1
0320 ADON
— ADSIDL ADDMABM —
AD12B
FORM<1:0>
SSRC<2:0>
AD1CON2
0322
VCFG<2:0>
—
— CSCNA
CHPS<1:0>
BUFS
—
AD1CON3
0324 ADRC
—
—
SAMC<4:0>
AD1CHS123 0326
—
—
—
—
—
CH123NB<1:0> CH123SB
—
—
—
AD1CHS0
0328 CH0NB —
—
CH0SB<4:0>
CH0NA
—
—
AD1PCFGL 032C —
—
—
—
—
—
—
—
—
—
PCFG5
AD1CSSL
0330
—
—
—
—
—
—
—
—
—
—
CSS5
AD1CON4
0332
—
—
—
—
—
—
—
—
—
—
—
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
SIMSAM ASAM SAMP DONE
SMPI<3:0>
BUFM ALTS
ADCS<7:0>
—
—
CH123NA<1:0> CH123SA
CH0SA<4:0>
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
CSS4
CSS3
CSS2 CSS1 CSS0
—
—
DMABL<2:0>
xxxx
0000
0000
0000
0000
0000
0000
0000
0000