70291E Datasheet, PDF (53/436 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

TABLE 4-12: I2C1 REGISTER MAP
SFR Name
SFR
Addr
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
0200
—
—
—
—
—
—
—
—
0202
—
—
—
—
—
—
—
—
0204
—
—
—
—
—
—
—
0206 I2CEN
—
I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN
0208 ACKSTAT TRSTAT
—
—
—
BCL GCSTAT ADD10 IWCOL
020A
—
—
—
—
—
—
020C
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 5
Bit 4
Bit 3
Receive Register
Transmit Register
Baud Rate Generator Register
STREN ACKDT ACKEN RCEN
I2COV
D_A
P
S
Address Register
Address Mask Register
Bit 2
PEN
R_W
Bit 1
RSEN
RBF
Bit 0
SEN
TBF
All
Resets
0000
00FF
0000
1000
0000
0000
0000
TABLE 4-13: UART1 REGISTER MAP
SFR Name
SFR
Addr
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
0220 UARTEN
—
USIDL IREN RTSMD
—
UEN1 UEN0 WAKE LPBACK
0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT
URXISEL<1:0>
0224
—
—
—
—
—
—
—
UTX8
0226
—
—
—
—
—
—
—
URX8
0228
Baud Rate Generator Prescaler
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD URXINV BRGH
ADDEN RIDLE PERR
UART Transmit Register
UART Received Register
PDSEL<1:0>
FERR OERR
Bit 0
STSEL
URXDA
All
Resets
0000
0110
xxxx
0000
0000
TABLE 4-14: UART2 REGISTER MAP
SFR Name
SFR
Addr
Bit 15
Bit 14 Bit 13
Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
Legend:
0230 UARTEN
—
USIDL IREN RTSMD
—
UEN1 UEN0 WAKE LPBACK
0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT
URXISEL<1:0>
0234
—
—
—
—
—
—
—
UTX8
0236
—
—
—
—
—
—
—
URX8
0238
Baud Rate Generator Prescaler
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 5
Bit 4
Bit 3
ABAUD URXINV BRGH
ADDEN RIDLE PERR
UART Transmit Register
UART Receive Register
Bit 2
Bit 1
PDSEL<1:0>
FERR OERR
Bit 0
STSEL
URXDA
All
Resets
0000
0110
xxxx
0000
0000