70291E Datasheet, PDF (154/436 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
REGISTER 9-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER⁽¹⁾
U-0
—
bit 15
U-0
R/W-0
R/W-0
R/W-0
—
SELACLK
AOSCMD<1:0>
R/W-0
R/W-0
APSTSCLR<2:0>
R/W-0
bit 8
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
ASRCSEL
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6-0
Unimplemented: Read as ‘0’
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider
1 = Auxiliary Oscillators provides the source clock for Auxiliary Clock Divider
0 = PLL output (FVCO) provides the source clock for the Auxiliary Clock Divider
AOSCMD<1:0>: Auxiliary Oscillator Mode
11 = EC External Clock Mode Select
10 = XT Oscillator Mode Select
01 = HS Oscillator Mode Select
00 = Auxiliary Oscillator Disabled (default)
APSTSCLR<2:0>: Auxiliary Clock Output Divider
111 = divided by 1
110 = divided by 2
101 = divided by 4
100 = divided by 8
011 = divided by 16
010 = divided by 32
001 = divided by 64
000 = divided by 256 (default)
ASRCSEL: Select Reference Clock Source for Auxiliary Clock
1 = Primary Oscillator is the Clock Source
0 = Auxiliary Oscillator is the Clock Source
Unimplemented: Read as ‘0’
Note 1: This register is reset only on a Power-on Reset (POR).
DS70291E-page 154
© 2011 Microchip Technology Inc.