PIC16LF1508 Datasheet, PDF (376/384 Pages) Microchip Technology – 20-Pin Flash, 8-Bit Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1508/9
CMxCON1 Register .......................................................... 160
Code Examples
A/D Conversion ......................................................... 140
Initializing PORTA ..................................................... 113
Writing to Flash Program Memory ............................ 104
Comparator
Associated Registers ................................................ 161
Operation .................................................................. 153
Comparator Module .......................................................... 153
Cx Output State Versus Input Conditions ................. 155
Comparator Specifications ................................................ 349
Comparators
C2OUT as T1 Gate ................................................... 169
Complementary Waveform Generator (CWG) .......... 297, 298
CONFIG1 Register.............................................................. 44
CONFIG2 Register.............................................................. 45
Core Function Register ....................................................... 28
Customer Change Notification Service ............................. 381
Customer Notification Service........................................... 381
Customer Support ............................................................. 381
CWG
Auto-shutdown Control ............................................. 304
Clock Source............................................................. 300
Output Control........................................................... 300
Selectable Input Sources .......................................... 300
CWGxCON0 Register ....................................................... 307
CWGxCON1 Register ....................................................... 308
CWGxCON2 Register ....................................................... 309
CWGxDBF Register .......................................................... 310
CWGxDBR Register.......................................................... 310
D
DACCON0 (Digital-to-Analog Converter Control 0)
Register..................................................................... 152
DACCON1 (Digital-to-Analog Converter Control 1)
Register..................................................................... 152
Data Memory....................................................................... 20
DC and AC Characteristics ............................................... 357
DC Characteristics
Extended and Industrial ............................................ 338
Industrial and Extended ............................................ 331
Development Support ....................................................... 359
Device Configuration........................................................... 43
Code Protection .......................................................... 46
Configuration Word ..................................................... 43
User ID .................................................................. 46, 47
Device ID Register .............................................................. 47
Device Overview ............................................................. 9, 91
Digital-to-Analog Converter (DAC).................................... 149
Associated Registers ................................................ 152
Effects of a Reset...................................................... 150
Specifications ............................................................ 349
E
Effects of Reset
PWM mode ............................................................... 267
Electrical Specifications .................................................... 329
Enhanced Mid-Range CPU................................................. 15
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)............................... 237
Errata .................................................................................... 8
EUSART............................................................................ 237
Associated Registers
Baud Rate Generator........................................ 250
Asynchronous Mode ................................................. 239
12-bit Break Transmit and Receive................... 257
Associated Registers
Receive .................................................... 245
Transmit.................................................... 241
Auto-Wake-up on Break ................................... 255
Baud Rate Generator (BRG) ............................ 249
Clock Accuracy................................................. 246
Receiver ........................................................... 242
Setting up 9-bit Mode with Address Detect ...... 244
Transmitter ....................................................... 239
Baud Rate Generator (BRG)
Auto Baud Rate Detect..................................... 254
Baud Rate Error, Calculating............................ 249
Baud Rates, Asynchronous Modes .................. 251
Formulas........................................................... 250
High Baud Rate Select (BRGH Bit) .................. 249
Synchronous Master Mode............................... 258, 262
Associated Registers
Receive .................................................... 261
Transmit.................................................... 259
Reception ......................................................... 260
Transmission .................................................... 258
Synchronous Slave Mode
Associated Registers
Receive .................................................... 263
Transmit.................................................... 262
Reception ......................................................... 263
Transmission .................................................... 262
Extended Instruction Set
ADDFSR ................................................................... 319
F
Fail-Safe Clock Monitor ...................................................... 60
Fail-Safe Condition Clearing....................................... 60
Fail-Safe Detection ..................................................... 60
Fail-Safe Operation..................................................... 60
Reset or Wake-up from Sleep .................................... 60
Firmware Instructions ....................................................... 315
Fixed Voltage Reference (FVR)........................................ 131
Associated Registers ................................................ 132
Flash Program Memory ...................................................... 95
Associated Registers ................................................ 110
Configuration Word w/ Flash Program Memory........ 110
Erasing ....................................................................... 99
Modifying .................................................................. 105
Write Verify ............................................................... 107
Writing ...................................................................... 101
FSR Register ...................................................................... 28
FVRCON (Fixed Voltage Reference Control) Register..... 132
I
I²C Mode (MSSPx)
Acknowledge Sequence Timing ............................... 222
Bus Collision
During a Repeated Start Condition................... 227
During a Stop Condition ................................... 228
Effects of a Reset ..................................................... 223
I²C Clock Rate w/BRG.............................................. 230
Master Mode
Operation.......................................................... 214
Reception ......................................................... 220
Start Condition Timing .............................. 216, 217
Transmission .................................................... 218
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 223
Multi-Master Mode .................................................... 223
Read/Write Bit Information (R/W Bit) ........................ 198
DS41609A-page 376
Preliminary
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