PIC16LF1508 Datasheet, PDF (272/384 Pages) Microchip Technology – 20-Pin Flash, 8-Bit Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1508/9
24.1 CLCx Setup
Programming the CLCx module is performed by config-
uring the 4 stages in the logic signal flow. The 4 stages
are:
• Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
24.1.1 DATA SELECTION
There are 16 signals available as inputs to the configu-
rable logic. Four 8-input multiplexers are used to select
the inputs to pass on to the next stage. The 16 inputs to
the multiplexers are arranged in groups of four. Each
group is available to two of the four multiplexers, in
each case, paired with a different group. This arrange-
ment makes possible selection of up to two from a
group without precluding a selection from another
group.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers (Register 24-3 and Register 24-4,
respectively).
Data inputs are selected with CLCxSEL0 and
CLCxSEL1 registers (Register 24-3 and Register 24-4,
respectively).
Data selection is through four multiplexers as indicated
on the left side of Figure 24-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 24-1 correlates the generic input name to the
actual signal for each CLC module. The columns labeled
lcxd1 through lcxd4 indicate the MUX output for the
selected data input. D1S through D4S are abbreviations
for the MUX select input codes: LCxD1S<2:0> through
LCxD4S<2:0>, respectively. Selecting a data input in a
column excludes all other inputs in that column.
Note: Data selections are undefined at power-up.
TABLE 24-1: CLCx DATA INPUT SELECTION
Data Input
lcxd1 lcxd2 lcxd3 lcxd4
D1S D2S D3S D4S
CLC 1
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
000 —
— 100 CLC1IN0
001 —
— 101 CLC1IN1
010 —
— 110 SYNCC1OUT
011 —
— 111 SYNCC2OUT
100 000 —
— FOSC
101 001 —
— TMR0IF
110 010 —
— TMR1IF
111 011 —
— TMR2 = PR2
— 100 000 — lc1_out
— 101 001 — lc2_out
— 110 010 — lc3_out
— 111 011 — lc4_out
—
— 100 000 NCO1OUT
—
— 101 001 HFINTOSC
—
— 110 010 PWM3OUT
—
— 111 011 PWM4OUT
CLC 2
CLC2IN0
CLC2IN1
SYNCC1OUT
SYNCC2OUT
FOSC
TMR0IF
TMR1IF
TMR2 = PR2
lc1_out
lc2_out
lc3_out
lc4_out
LFINTOSC
ADFRC
PWM1OUT
PWM2OUT
CLC 3
CLC3IN0
CLC3IN1
SYNCC1OUT
SYNCC2OUT
FOSC
TMR0IF
TMR1IF
TMR2 = PR2
lc1_out
lc2_out
lc3_out
lc4_out
TX (EUSART)
LFINTOSC
PWM2OUT
PWM3OUT
CLC 4
CLC4IN0
CLC4IN1
SYNCC1OUT
SYNCC2OUT
FOSC
TMR0IF
TMR1IF
TMR2 = PR2
lc1_out
lc2_out
lc3_out
lc4_out
SCK (MSSP)
SDO (MSSP)
PWM1OUT
PWM4OUT
DS41609A-page 272
Preliminary
 2011 Microchip Technology Inc.