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PIC16LF1508 Datasheet, PDF (233/384 Pages) Microchip Technology – 20-Pin Flash, 8-Bit Microcontrollers with nanoWatt XLP Technology | |||
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PIC16(L)F1508/9
REGISTER 21-3: SSPXCON2: SSP CONTROL REGISTER 2
R/W-0/0
GCEN
bit 7
R-0/0
ACKSTAT
R/W-0/0
ACKDT
R/S/HS-0/0 R/S/HS-0/0
ACKEN
RCEN
R/S/HS-0/0
PEN
R/S/HS-0/0
RSEN
R/W/HS-0/0
SEN
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
â1â = Bit is set
W = Writable bit
x = Bit is unknown
â0â = Bit is cleared
U = Unimplemented bit, read as â0â
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
ï£ 2011 Microchip Technology Inc.
Preliminary
DS41609A-page 233
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