PIC16LF1508 Datasheet, PDF (286/384 Pages) Microchip Technology – 20-Pin Flash, 8-Bit Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1508/9
TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Name
Bit7
Bit6
Bit5
Bit4
BIt3
Bit2
Bit1
Bit0
Register
on Page
ANSELC
ANSC7
ANSC6
—
—
ANSC3
ANSC2
ANSC1
ANSC0
123
APFCON
—
—
—
SSSEL
T1GSEL
—
CLC1SEL NCO1SEL
112
CLC1CON
LC1EN
LC1OE
LC1OUT LC1INTP LC1INTN
LC1MODE<2:0>
277
CLC2CON
LC2EN
LC2OE
LC2OUT LC2INTP LC2INTN
LC2MODE<2:0>
277
CLCDATA
—
—
—
—
MLC4OUT MLC3OUT MLC2OUT MLC1OUT 281
CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 281
CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 282
CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 283
CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 284
CLC1POL
LC1POL
—
—
—
LC1G4POL LC1G3POL LC1G2POL LC1G1POL 278
CLC1SEL0
—
LC1D2S<2:0>
—
LC1D1S<2:0>
279
CLC1SEL1
—
LC1D4S<2:0>
—
LC1D3S<2:0>
280
CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 281
CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 282
CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 283
CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 284
CLC2POL
LC2POL
—
—
—
LC2G4POL LC2G3POL LC2G2POL LC2G1POL 278
CLC2SEL0
—
LC2D2S<2:0>
—
LC2D1S<2:0>
279
CLC2SEL1
—
LC2D4S<2:0>
—
LC2D3S<2:0>
280
CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 281
CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 282
CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 283
CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 284
CLC3POL
LC3POL
—
—
—
LC3G4POL LC3G3POL LC3G2POL LC3G1POL 278
CLC3SEL0
—
LC3D2S<2:0>
—
LC3D1S<2:0>
279
CLC3SEL1
—
LC3D4S<2:0>
—
LC3D3S<2:0>
280
CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N 281
CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 282
CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 283
CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N 284
CLC4POL
LC4POL
—
—
—
LC4G4POL LC4G3POL LC4G2POL LC4G1POL 278
CLC4SEL0
—
LC4D2S<2:0>
—
LC4D1S<2:0>
279
CLC4SEL1
—
LC4D4S<2:0>
—
LC4D3S<2:0>
280
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
78
PIE3
—
—
—
—
CLC4IE CLC3IE CLC2IE CLC1IE
81
PIR3
TRISA
—
—
—
—
CLC4IF CLC3IF CLC2IF CLC1IF
84
—
—
TRISA5
TRISA4
—⁽¹⁾
TRISA2
TRISA1
TRISA0
114
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
122
Legend: — = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.
Note 1: Unimplemented, read as ‘1’.
DS41609A-page 286
Preliminary
 2011 Microchip Technology Inc.