PIC16LF1847 Datasheet, PDF (33/408 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1847
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bank 4
200h⁽¹⁾ INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
201h⁽¹⁾ INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
202h⁽¹⁾ PCL
Program Counter (PC) Least Significant Byte
203h⁽¹⁾ STATUS
—
—
—
TO
PD
Z
DC
204h⁽¹⁾ FSR0L
Indirect Data Memory Address 0 Low Pointer
205h⁽¹⁾ FSR0H
Indirect Data Memory Address 0 High Pointer
206h⁽¹⁾ FSR1L
Indirect Data Memory Address 1 Low Pointer
207h⁽¹⁾ FSR1H
Indirect Data Memory Address 1 High Pointer
208h⁽¹⁾ BSR
—
—
—
BSR4
BSR3
BSR2
BSR1
209h⁽¹⁾ WREG
Working Register
20Ah⁽¹⁾ PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
20Bh⁽¹⁾ INTCON
GIE
PEIE
TMR0IE
INTE
IOCE
TMR0IF
INTF
20Ch
WPUA
—
—
WPUA5
—
—
—
—
20Dh
WPUB
WPUB7
WPUB6
WPUB5
WPUB4 WPUB3 WPUB2 WPUB1
20Eh
—
Unimplemented
20Fh
—
Unimplemented
210h
—
Unimplemented
211h
212h
213h
SSP1BUF
SSP1ADD
SSP1MSK
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I²C mode) Address Register
Synchronous Serial Port (I²C mode) Address Mask Register
214h
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
215h
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3 SSPM2 SSPM1
216h
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
217h
SSP1CON3 ACKTIM
PCIE
SCIE
BOEN
SDAHT SBCDE
AHEN
218h
—
Unimplemented
219h
21Ah
21Bh
SSP2BUF
SSP2ADD
SSP2MSK
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I²C mode) Address Register
Synchronous Serial Port (I²C mode) Address Mask Register
21Ch
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
21Dh
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3 SSPM2 SSPM1
21Eh
SSP2CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
21Fh
SSP2CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT SBCDE
AHEN
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
C
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
BSR0 ---0 0000 ---0 0000
0000 0000 uuuu uuuu
IOCF
—
WPUB0
-000 0000 -000 0000
0000 000x 0000 000u
--1- ---- --1- ----
1111 1111 1111 1111
—
—
—
—
—
—
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
BF
SSPM0
SEN
DHEN
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
—
—
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
BF
SSPM0
SEN
DHEN
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
 2011 Microchip Technology Inc.
Preliminary
DS41453A-page 33