PIC16LF1847 Datasheet, PDF (243/408 Pages) Microchip Technology – 18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1847
25.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL
ANSELA
—
—
—
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
ANSELB
ANSB7
ANSB6
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
—
INTCON
GIE
PEIE
TMR0IE
INTE
IOCE
TMR0IF
INTF
IOCF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF TMR2IF TMR1IF
SSP1BUF _{Synchronous Serial Port Receive Buffer/Transmit Register}
SSP1CON1 WCOL
SSPOV
SSPEN
CKP
SSPM<3:0>
SSP1CON3 ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSP1STAT
SMP
CKE
D/A
P
S
SSP2BUF Synchronous Serial Port Receive Buffer/Transmit Register
R/W
UA
BF
SSP2CON1 WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SSP2CON3 ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSP2STAT
TRISA
SMP
TRISA7
CKE
TRISA6
D/A
TRISA5
P
TRISA4
S
TRISA3
R/W
TRISA2
UA
TRISA1
BF
TRISA0
TRISB
Legend:
*
TRISB7
TRISB6
TRISB5 TRISB4
TRISB3
TRISB2 TRISB1 TRISB0
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
Page provides register information.
Register
on Page
120
123
128
89
90
94
237*
283
285
282
29
283
285
282
122
127
 2011 Microchip Technology Inc.
Preliminary
DS41453A-page 243