MAX1463 Datasheet, PDF (7/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 5.0V, V_SS = 0V, T_A = T_MIN to T_MAX, f_CLK = 4.0MHz. Typical values are at T_A = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
DIGITAL INPUT (GPIO1, GPIO2, SCLK, DI, CKSEL, CKIO, CS)
MIN TYP MAX
Input High Threshold Voltage
V_IH
0.8 x
V_DD
Input Low Threshold Voltage
V_IL
Input Hysteresis
V_IHYS
Input Leakage Current
CKSEL, CS = V_SS
I_IN
GPIO1, GPIO2, SCLK, DI, CKIO = V_DD
Input Capacitance
C_IN
DIGITAL OUTPUT (GPIO1, GPIO2, DO, CKIO)
0.2 x
V_DD
0.2
-50
50
5
Output Voltage High
Output Voltage Low
GPIO1, GPIO2, DO
4.9
R_LOAD = ∞
CKIO (Note 10)
4.9
V_OH
GPIO1, GPIO2, DO
4.6
R_LOAD = 2kΩ to V_{SS CKIO (Note 10)}
4.6
GPIO1, GPIO2, DO
R_LOAD = ∞
CKIO (Note 10)
V_OL
GPIO1, GPIO2, DO
R_LOAD = 2kΩ to V_{DD CKIO (Note 10)}
0.1
0.1
0.4
0.4
FLASH MEMORY
Maximum Erase Cycles
(Notes 11, 12)
10K
Minimum Erase Time
t_ERASE (Notes 11, 12)
4.2
Minimum Write Time
t_WRITE (Notes 11, 12)
80
UNITS
V
V
V
µA
pF
V
V
Cycles
ms
µs
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to V_SS.
All modules are off, except internal reference, oscillator, VBG buffer, and power-on reset (POR). ISRC is open.
The CPU and ADC are not on at the same time. The ADC and CPU currents are not additive.
I_DACn does not include output buffer currents (I_OPLGn or I_OPSMn).
For gains above 240, an additional digital gain can be provided by the CPU.
The PWM input data is the 12-bit left-justified data in the 16-bit input field.
PWM gain error measured as:
GE_PWM
=
PWM_OUT(F00Xh₎ − PWM_OUT(100Xh₎
3584
× 100%
Note 8: The Internal Reference Voltage has a nominal value of 5V (4 ✕ V_BG) even when V_DD is greater or less than 5VDC.
Note 9: Input-referred offset error is the ADC Offset Error divided by the PGA gain.
Note 10: When the CKIO pin is configured in output mode to observe the internal oscillator signal, the total current is above the
specified limits.
Note 11: f_CLK must be within 5% of 4MHz.
Note 12: Allow a minimum elapsed time of 4.2ms when executing a FLASH erase command, before sending any other command.
Allow a minimum elapsed time of 80µs between FLASH write commands.
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