MAX1463 Datasheet, PDF (18/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
SW0
SW10
SM
SW3
OUTnSM
AMPnM
AMPnP
SW2
SW1
SW4
SW8
SW6
SW7
OUTnLG
SW9
LG
SW11
SW5
REF
DAC
PWM
VDD
VREF X 2
10h OR 13h
11h OR 14h
12h OR 15h
DOPn_DATA
DOPn_CONTROL
DOPn_CONFIG
30h
OPAMP_CONFIG
Figure 5. DOP1 and DOP2 Modules
Either the small or the large op amp in the DOP module
can also be selected as an uncommitted op amp in the
MAX1463. The op amps can be configured as a unity-
gain buffer, where the output is internally connected to the
negative terminal of the op amp, or a stand-alone op amp,
where both AMPnM and AMPnP can be externally con-
nected for various analog functions. In the case of a
buffer, the device pin AMPnM is in high-impedance mode,
as the feedback loop around the op amp is connected
internally.
Every function of the DOP module can be selected individ-
ually (DAC, PWM, or op amp), or two out of the three func-
tions of the DOP module can be selected at the same time
(PWM and op amp, or DAC and PWM, or DAC and op
amp), as there are only two output pins for the module,
OUTnSM and OUTnLG. The various configuration options
for the DOP are shown in Table 21. The PWRDAC and
PWROP bits are in the power-on control register (address
= 31h), and the remaining bits are in the DOP registers.
Timer Module
The timer module (Figure 6) comprises a 12-bit counter, a
4-bit prescalar, and control and configuration registers.
When the timer is enabled and initiated, the system master
clock, MCLK, is prescaled by the divisor set by PS[3:0] in
the TMR_Config register and the result applied to the 12-
bit upcounter. When the counter value matches the time-
out value TO[11:0] in register TMR_Config, bit TMDN is set
to 1. The CPU can poll the timer done bit TMDN to check
its status.
The timer module provides a feature that enables the CPU
to be put into a low-power halt mode for the duration of the
timer interval. Setting the ENAHALT bit in the TMR_Control
register while starting the timer (setting the timer enable bit
TMEN to 1), or while the timer is already enabled and
counting halts the CPU at the present instruction until the
TMDN bit becomes set by the counter. The CPU com-
mences execution with the next instruction. All CPU regis-
ters and ports are fully static and retain all data during the
elapsed time interval.
The time interval between TMEN being set to 1, and
TMDN being set to 1 can be computed as follows:
Time Interval = (2 / F_OSC) x {(prescale value N)
x (timeout value TO[11:0]) + 1.5}
The maximum time interval given F_OSC = 4MHz clock is
786ms.
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