MAX1463 Datasheet, PDF (21/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
CS
SCLK
IRS0
IRS1
DI
IRSA0
IRSA1
Figure 9. Serial Interface Data Input
IRS2
IRSA2
IRS3
IRSA3
IRS4
IRSD0
IRS5
IRSD1
IRS6
IRSD2
IRS7
IRSD3
CS
SCLK
DI
DO
IRS0
IRSA0
DHR15
IRS1
IRSA1
DHR14
IRS2
IRSA2
DHR13
IRS3
IRSA3
DHR12
IRS4
IRSD0
DHR11
IRS5
IRSD1
DHR10
IRS6
IRSD2
DHR9
IRS7
IRSD3
DHR8
IRS0
IRSA0
DHR7
IRS1
IRSA1
DHR6
IRS2
IRSA2
DHR5
IRS3
IRSA3
DHR4
IRS4
IRSD0
DHR3
IRS5
IRSD1
DHR2
IRS6
IRSD2
DHR1
IRS7
IRSD3
DHR0
Figure 10. 4-Wire Mode Data Read from DHR Register
These two FLASH memory locations are separated as
partitions. The program/coefficient memory is FLASH
partition 0 and the information memory is FLASH parti-
tion 1. Each partition is accessible by the serial inter-
face for reading, erasing, and writing data.
Program/coefficient memory partition 0 is accessible by
the CPU as read only, and partition 1 is not accessible
by the CPU. The CPU cannot erase or write data to
either of the FLASH memory partitions.
FLASH partition 0 is selected during the POR cycle.
FLASH partition 1 is selected by sending the halt CPU
command (IRS[7:0]=78h) and changing the partition
selected by sending the change partition command
(IRS[7:0]=F8h). A following halt command (IRS[7:0]=78h)
resets the selected partition to partition 0.
Modifying the FLASH Contents
The MAX1463 FLASH memory contents must be erased
(contents = FFh) before the desired contents can be writ-
ten. There is no individual byte-erase command, but
either a total-erase command (IRS[7:0]=E8h) where all
the selected partition is erased (4kB for partition 0 or 128
bytes for partition 1) or a page-erase command
(IRS[7:0]=D8h), where only 64 bytes are erased, and the
page is selected by PFAR[11:6]. There are 64 pages in
FLASH partition 0, and only 2 pages in FLASH partition 1.
The programming of the MAX1463 FLASH memory
must follow the procedure below (all the commands are
to be sent through the serial interface, and are hexa-
decimal values of IRS[7:0]):
1) Halt the CPU:
78.
2) If partition 1 is to be modified, enter the following
command:
F8
otherwise, partition 0 is selected.
3) Enable the PWRWFL bit on the power-on control
register:
13 02 01 00
(write 1000h to DHR[15:0])
D4
(write Dh to PFAR[3:0])
08
(write DHR, 1000h to CPU port
pointed by PFAR[3:0], port D)
03 02 31 10
(write 0031h to DHR[15:0])
E4
(write Eh to PFAR[3:0])
08
(write DHR, 0031h to CPU port
pointed by PFAR[3:0], port E)
83 02 01 00
(write 8000h to DHR[15:0])
F4
(write Fh to PFAR[3:0])
08
(write DHR, 8000h to CPU port
pointed by PFAR[3:0], port F)
At this point, all of the MAX1463 analog modules
are off. Only the bit that enables writing to the
FLASH is enabled.
4) For erasing the whole partition, send the following
command:
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