MAX1463 Datasheet, PDF (23/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
CS
SCLK
DI
10011000
DO
IRSA0 IRSA1 IRSA2 IRSA3 IRSD0 IRSD1 IRSD2 IRSD3
DHR15 DHR14 DHR13 DHR12 DHR11 DHR10 DHR9 DHR8 DHR7 DHR6 DHR5 DHR4 DHR3 DHR2 DHR1 DHR0
Figure 11. 3-Wire Mode Data Read from DHR Register
Although both the CPU and the serial interface can
address a 16-bit field, the flash size only uses 12 bits.
Therefore, the leading 4 MSBs of the address field are
ignored. It is advisable to have all leading bits of the
16-bit address in PFAR[15:0] set to zero.
The FLASH memory in partition 0 can be erased in indi-
vidual 64-byte pages using the page-erase command,
or erased in bulk using the all-erase command. The
information data memory (partition 1) is unaffected by
any operation performed on partition 0.
Information Data Memory
The information data memory, FLASH partition 1, is
addressed by bytes sequentially from 00h (0) to 7Fh
(127). The addressed byte should have all leading bits of
the 16-bit address in PFAR[15:0] set to zero.
The FLASH memory in partition 1 has only two 64-byte
pages that can be erased separately using the page-
erase command, or erased together using the all-erase
command. Data in partition 0 is not affected by any
operation performed on partition 1.
MAX1463 CPU Instruction Set
The MAX1463 CPU has 16 instructions used to perform
all calculations for sensor compensation, linearization,
and signal output functions. Each instruction comprises
a 4-bit op code and a 4-bit CPU register address. The
op code describes what operation to perform; the reg-
ister address describes what register, or registers, to
perform the operation on.
Instruction Format
All instructions are single-byte instructions with the
exception of load data from instruction memory. LDX
fetches the 2 following bytes of instruction memory and
loads them into a register. This is how calibration and
compensation coefficients are stored within the
MAX1463. Any number of coefficients can be stored in
instruction memory. The instruction code format is as
follows:
COMMAND OP-CODE
(BITS 7–4)
Bit 7 Bit 6 Bit 5 Bit 4
MSB
REGISTER OP CODE
(BITS 3–0)
Bit 3 Bit 2 Bit 1 Bit 0
LSB
Instruction Set Details
LDX
Load Register X
Op-code:
0000 XXXX_BINARY 0Xh
Operation:
X-register ← [PC+1] : [PC+2]
PC-register ← PC + 3 (point to next instruction)
CPU Cycles required:
3 cycles
Instruction:
Loads the next 2 bytes of program memory into CPU
register X. Register X can be any of the 16 CPU regis-
ters. Program counter (PC) is incremented twice during
the fetches of the next 2 bytes and incremented a third
time to point to the next instruction in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
CLX
Clear Register X
Op-code:
0001 XXXX_BINARY 1Xh
Operation:
X-register ← 0000h
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Clear the contents of register X to 0000h.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
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