MAX1463 Datasheet, PDF (25/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
SLX
Op-code:
Shift Left Register X
0110 XXXX_BINARY 6Xh
Operation when X ≠ 6h:
REGISTER X
0
BIT : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Operation when X = 6h:
REGISTER R6
BIT : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGISTER M: R4
BIT : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit shift-left operation on the contents of
X-register. The most significant bit, bit 15, is truncated
and lost. If register X is any CPU register other than
register R6, then a zero is appended into the LSB, bit 0.
If X is CPU register R6, then the data appended into the
LSB bit 0 is copied from the MSB of register R4. The
contents of register R4 are not affected. The operation
does not preserve the two’s complement sign bit-15.
The operation is equivalent to an arithmetic multiplica-
tion by 2 on an unsigned integer value stored in regis-
ter X. The result is stored back into X-register.
The previous contents of X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is not preserved.
No branching occurs.
No other registers are affected.
SRX
Shift Right Register X
Op-code: 0111 XXXX_BINARY 7Xh
Operation
REGISTER X
BIT : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 15-bit shift-right operation on the contents of
X-register, preserving the contents of the two’s comple-
ment sign bit-15 and propagating the sign bit, bit-15,
into bit-14. The least significant bit, bit 0, is truncated
and lost. The operation is equivalent to an arithmetic
division by 2. The result is stored back into X-register.
The previous contents of X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s complement data format is preserved.
No branching occurs.
No other registers are affected.
INX
Increment Register X
Op-code:
1000 XXXX_BINARY 8Xh
Operation:
X-register ← X-register + 1
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit increment operation on the contents of
X-register. Should the increment result in an overflow,
the overflow bit is truncated and lost. The result is
stored back into X-register.
The previous contents of X-register are overwritten
and lost.
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