MAX1463 Datasheet, PDF (16/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
Upon completion of the conversion, the ADC result is
latched into the respective ADC_Data_n register. In
addition, the convert bits in control register 0 are all
reset to zero. The CPU clock is then enabled and pro-
gram execution continues
Single-ended inputs can be converted by either chan-
nel 1 or 2 by initiating a conversion on the appropriate
channel with the SE[3:0] bits set to the desired single-
ended input (Table 7). Several of the single-ended sig-
nals are converted with a fixed gain of 0.94V/V or
0.7V/V. The reduced gain of 0.7V/V allows signals at or
near the supply rails to be converted without concern of
saturation. Other single-ended signals can be convert-
ed with the full-selectable PGA gain range.
Programmable Gain Amplifier
The gain of the differential inputs and several single-
ended inputs can be set to values between 0.94V/V to
240V/V as shown in Table 14. The PGA bits are set in
ADC_Config_nA where n = 1 or 2. The temperature
channel has a fixed gain of 0.94V/V. The gain setting
must be selected prior to initiating a conversion.
ADC Conversion Time and Resolution
The ADC conversion time is a function of the selected
resolution, ADC clock (F_ADC), and system clock (f_CLK).
The resolution can be selected from 9 bits to 16 bits in
the ADC_Config_nA (where n = 1, 2, or T) register by
bits RESn[2:0]. The lower resolution settings (9 bit) con-
vert faster than the higher resolution settings (16 bit).
The ADC clock F_ADC is derived from the primary sys-
tem clock F_CLK by a prescalar divisor. The divisor can
be set from 4 to 512, producing a range of F_ADC from
1MHz down to 7.8125kHz when F_CLK is operating at
4.0MHz. Other values of F_CLK produce other scaled
values of F_ADC.
Systems operating with very-low power consumption
benefit from the reduced F_ADC clock rate. Slower clock
speeds require less operating current. Systems operat-
ing from a larger power consumption budget can use
the highest F_ADC clock rate to improve speed perfor-
mance over power performance.
The ADC conversion times for various resolution and
clock-rate settings are summarized in Table 17. The
conversion time is calculated by the formula:
T_CONVERT = (no. of F_ADC clocks per conversion) /
F_ADC
Coarse-Input Offset Adjustment
Differential input signals that have an offset can be par-
tially nulled by the input CO DAC. An offset voltage is
added to the input signal prior to gaining the signal. This
allows a maximum gain to be applied to the differential
input signal without saturating the conversion channel.
The CO signal added to the differential signal is a per-
centage of the full-scale ADC reference voltage as
referred to the ADC inputs. Low PGA gain settings add
smaller amounts of coarse offset to the differential input.
Large PGA gain settings enable correspondingly larger
amounts of coarse offset to be added to the input signal.
The CO DAC also applies to the temperature channel
enabling offset compensation of the temperature signal.
Bias Current Settings
The analog circuitry within the ADC module operates
from a current bias setting that is programmable. The
programmable levels of operation are fractions of the
full bias current. The operating power consumption of
the ADC can be reduced at the penalty of increased
conversion times that may be desirable in very-low-
power applications. It is recommended operating the
ADC at full bias when possible. The amount of bias as
a fraction of full bias is shown in Table 19. The setting is
controlled by the BIASn[2:0] bits in the ADC_CON-
FIG_nB registers where n = 1, 2, or T.
Reference Input Voltage Select
The ADC can use one of three different reference volt-
age inputs depending on the conversion channel and
REFn setting as shown in Table 20. The differential
inputs can be converted ratiometrically to the supply
voltage (V_DD), converted ratiometrically to an externally
supplied voltage at pin VREF, or converted nonratio-
metrically using a fixed voltage source derived from the
internal bandgap voltage source. The temperature
channel is always converted using the internal bandgap-
derived voltage source and therefore is not selectable.
Output Sample Rate
Generally, the sensor and temperature data are convert-
ed and calculated by an algorithm in the execution loop.
The output sample rate of the data depends on the con-
version time, the CPU algorithm loop time, and the time to
store the result in the DOPn_DATA register. To achieve
uniform sampling, the instruction code must be written to
provide a consistent algorithm loop time, including
branch instruction variations. This total loop time interval
should be repeatable for a uniform output rate.
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