MAX1463 Datasheet, PDF (17/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
The MAX1463 has a built-in timer that can be used to
ensure that the sampling interval is uniform. The time-
out value can be set such that the CPU computations
and the reading of the serial interface, if required, can
be completed before timeout. The GPIO pins can be
utilized to interrupt an external master microcontroller
when the ADC conversion is done and/or when the
CPU computations are done so that the serial interface
can be read quickly.
DAC, Op Amp, PWM Modules (DOPn)
There are two output modules in the MAX1463—DOP1
and DOP2 (Figure 5). Each of the DOP modules con-
tains a 16-bit DAC, a 12-bit digital PWM converter, a
small op amp, and a large op amp with high-output
drive capability. Switches in the DOP module enable a
range of interconnectivity among the converters, op
amps, and the external pins. Either the DAC or the
PWM may be selected as the primary output signal.
The DAC output signal is routed to one of the op amps
and made available to a device pin. The signal-switch-
ing arrangement also allows the unused op amp to be
configured as an uncommitted device with all connec-
tions available to external pins.
The DAC and op amps have a power-control bit in the
power module. When power is disabled, all circuits in
the DAC and the op amp are disabled with inputs and
outputs in a three-state condition. The proper bits in the
power module must be enabled for operation of the
DAC and op amps.
The DAC input is a 16-bit two’s complement value. An
input value of 0000h produces an output voltage of one
half of the DAC reference voltage. The DAC output volt-
age increases for positive two’s complement numbers,
and decreases for negative two’s complement numbers.
The PWM input is a 12-bit two’s complement value. It
shares the same input register (DOPn_Data) as the
DAC, using the 12 MSBs of the 16-bit register. An input
value of 000Xh produces a 50% duty cycle waveform at
the output. The PWM output duty cycle increases for
positive two’s complement numbers, and decreases for
negative two’s complement numbers.
DOP_n Configuration Options
Each of the DOP modules can be configured in several
different modes to suit a wide range of output signal
requirements. The Functional Diagram shows the various
switch settings of the configuration and control registers.
In situations where configuration settings create a con-
flict in switch activation, a priority is applied to the switch
logic to prevent the conflict.
The DAC and/or the PWM can be selected as the out-
put signal source. The DAC output signal is routed to
one of the op amps and made available to a device
pin. Selecting the large op amp as the DAC output dri-
ver device enables a robust current drive capability for
driving signals into low-impedance loads or across
long lengths of wire. The unity-gain buffer configuration
is automatically selected, and it provides the DAC out-
put signal directly to the device pin OUTnLG. With the
large op amp selected, the small op amp can be used
as an independent device for external circuit applica-
tions when the PWM is disabled. Alternatively, the PWM
can also be enabled to drive the OUTnSM device pin,
in which case the small op amp is OFF.
Selecting the small op amp as the DAC output driver
device is useful for routing the output signal to other cir-
cuits in an embedded control system with high-imped-
ance load connections. The unity-gain buffer configuration
is automatically selected, and it provides the DAC output
signal directly to the device pin OUTnSM. With the small
op amp selected, the large op amp can be used as an
independent device for external circuit applications when
the PWM is disabled. Alternatively, the PWM can also be
enabled to drive the OUTnLG device pin, in which case
the large op amp is OFF.
The DAC has two reference voltage sources available
by selection, V_DD and VREF pin. When the external ref-
erence is selected (VREF), the actual DAC reference is
2 x VREF. This allows for some degree of flexibility in
the bit weight of the DAC. The output of the DAC is a
voltage proportional to the reference voltage selected,
where the proportionality scaling (DAC input) is set in
the data input register DOPn_Data.
The DOP module also provides a 12-bit digital PWM
output. At a nominal frequency of 4MHz, the frequency
of the PWM is 122Hz (PWM period = 8.192ms). The
DAC and the PWM share the same input register,
DOPn_Data, where the PWM uses the 12 MSBs, in
two’s-complement format. An input of 000Xh (4 LSBs
are ignored) outputs a 50% duty cycle waveform at the
selected output pin (either OUTnSM or OUTnLG). The
PWM bit weight is 2µs, at a nominal frequency of 4MHz.
The minimum duty cycle is obtained when the input is
800Xh (duty cycle is 0 / 4096 = 0), and the maximum
duty cycle at 7FFXh (duty cycle is 4095 / 4096 =
99.98%). A new PWM input word is only effective at the
end of a current PWM cycle, therefore preventing PWM
glitches on the output.
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