MAX1463 Datasheet, PDF (22/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
E8
otherwise, if only a page erase is required, first write
PFAR[11:6] with the page address, as:
07 X6 X5 04
(write 0XX0h to PFAR[15:0])
Note that the 2 lower bits of PFAR[7:4] should be
zero, and only the upper 2 bits of that nibble should
be set to the desired value. Then, after writing the
page address, send the page-erase command:
D8
5) Wait at least 4.2ms before sending any other com-
mand to allow the necessary time for the
erase operation to complete.
6) Write the address of the flash byte to be written to
PFAR[15:0]:
07 X6 X5 X4 (write 0XXXh to PFAR[15:0])
7) Write the contents of the byte to DHR[7:0]:
X1 X0
(write XXh to DHR[7:0], high nibble
at DHR[7:4])
8) Send the command to execute the FLASH write:
18
9) Repeat steps 6), 7), and 8) for all the bytes to be
written. It is not necessary to send the whole
address and data for every byte that is written. Only
the nibbles that are modified in the PFAR and in the
DHR from previous values must be changed. The
time interval between successive write commands
(18h) must be at least 80µs.
10) If partition 1 was selected in step 2), and the user
wants to switch back to partition 0, send the follow
ing command:
78
At this point, partition 0 is selected. The user may
want to go back to step 4) to program partition 0, or
just continue on.
11) Disable the PWRWFL bit:
03 02 01 00
(write 0000h to DHR[15:0])
D4
(write Dh to PFAR[3:0])
08
(write DHR, 0000h to CPU port
pointed by PFAR[3:0], port D)
03 02 31 10
(write 0031h to DHR[15:0])
E4
(write Eh to PFAR[3:0])
08
(write DHR, 0031h to CPU port
pointed by PFAR[3:0], port E)
83 02 01 00
(write 8000h to DHR[15:0])
F4
(write Fh to PFAR[3:0])
08
(write DHR, 8000h to CPU port
pointed by PFAR[3:0], port F)
Alternatively, you can send the reset command,
which also clears the PWRWFL bit:
B8
Reading the Flash Contents
The procedure to read the flash contents is no different
from reading any other information from the MAX1463.
The flash contents must be copied to the DHR and
read through the serial interface (all the commands are
hexadecimal values of IRS [7:0]):
1) If the CPU is not halted, halt the CPU:
78
2) If partition 1 is to be read, enter the following com-
mand:
F8
otherwise, partition 0 is selected.
3) Write the address of the flash byte to be read to
PFAR[15:0]:
07 X6 X5 X4 (write 0XXXh to PFAR[15:0])
4) Copy the contents of flash addressed by PFAR to
DHR:
38
5) If the interface is configured in 3-wire mode, send
19
to enable DO on the next CS cycle. Then three-
state the DI driver, and send 16 SCLK pulses on
the following CS cycle, and DO outputs DHR[15:0].
The flash data is present at DHR[7:0]. See Figure
11 for details.
If the interface is configured in 4-wire mode, there
is no need to enable the DO line, as it has already
been enabled by a previous IRS command 09h.
Send the 16 SCLK pulses and retrieve the data on
the DO line.
6) Repeat steps 3), 4), and 5) for every byte to be
read. Only the nibbles that are modified in the
PFAR register are required to be sent.
Program and Coefficient Memory
The program and coefficient memory, FLASH partition 0,
is addressed by the CPU and by the serial interface
sequentially from 0000h (0 dec) to 0FFFh (4095 dec).
Program execution by the CPU always begins at address
0000h and proceeds toward 0FFFh in 1-byte increments.
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