MAX1463 Datasheet, PDF (5/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

Low-Power Two-Channel Sensor
Signal Processor
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 5.0V, V_SS = 0V, f_CLK = 4.0MHz, T_A = T_MIN to T_MAX. Typical values are at T_A = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
LARGE OP AMP
Input Offset Voltage
Input Bias Current
V_OS__LG
I_B__LG
DC Gain
A_VOL__LG
OUTnLG = 0.5V to 4.5V (n = 1 or 2),
R_LOAD = ∞
Gain Bandwidth Product
Slew Rate
Common-Mode Input Range
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Input-Referred Noise Voltage
GBW__LG
SR__LG
CMR__LG
CMRR__LG
PSRR__LG
V_N__LG
A_{VOL_LG} = +1V/V
A_{VOL_LG} = +1V/V
V_{CM OPAMP} = V_SS to V_DD
At DC
0.1Hz to 1kHz
0.1Hz to 1MHz
Output High Voltage
Output Low Voltage
Output Source Current
Output Sink Current
Maximum Output Load
Capacitance
OP-AMP SWITCH
V_OH__LG
V_OL__LG
I_SRC__LG
I_SNK__LG
C_L__LG
R_LOAD = ∞
R_LOAD = 1kΩ to V_SS
R_LOAD = ∞
R_LOAD = 1kΩ to V_DD
V_OUTnLG = V_{OH_LG}, R_LOAD = 1kΩ to V_SS
V_OUTnLG = V_{OL_LG}, R_LOAD = 1kΩ to V_DD
R_LOAD = ∞, phase margin > 55°
Analog Signal Range
V_SW
On-Resistance
R_ON
Off-Isolation
V_ISO
DIGITAL-TO-ANALOG CONVERTER
Resolution
Integral Nonlinearity
Differential Nonlinearity
RES_DAC
INL_DAC
DNL_DAC
Offset Error
V_{DAC OS} DAC ref = V_DD, DAC data = 0000h
Bit Weight
Power-Supply Rejection Ratio
Output Noise
Output Settling Time
PULSE-WIDTH MODULATOR
Resolution
Period
BW_DAC
PSRR_DAC
ON_DAC
ST_DAC
DAC ref = 5VDC
At DC, DAC ref = V_REF
DAC buffer is the small op amp
To 0.1% of final value
RES_PWM (Note 6)
P_PWM f_CLK = 4.0 MHz
MIN TYP MAX UNITS
0
±4
mV
±225
nA
100
dB
4.0
MHz
3.2
V/µs
V_SS
V_DD
V
70
dB
70
dB
19
µV_RMS
160
4.95
V
4.90
0.03
V
0.12
-4.9
mA
4.9
mA
200
pF
V_SS
V_DD
V
5
kΩ
80
dB
V_DD / 2
- 0.05
16
3
±1
91.55
60
±3
250
V_DD / 2
+ 0.05
Bits
Bits
Bits
V
µV/LSB
dB
LSB
µs
12
Bits
8.192
ms
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