MAX1463 Datasheet, PDF(15/49 Page) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

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MAX1463 Datasheet, PDF (15/49 Pages) Maxim Integrated Products – Low-Power Two-Channel Sensor Signal Processor

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Low-Power Two-Channel Sensor

Signal Processor

INP1

INM1

INP2

INM2

VSS

TEMPERATURE

SENSOR

REF

Î£

PGA

VSS

NO.

SINGLE ENDED

1 VBG

2 OUTnSM

3 OUTnLG

VDD

VSS

6 DACnOUT VIA OUTnSM

7 DACnOUT VIA OUTnLG

8 INPn

9 INMn

VDD

VREF

VBG x 4

VBG

00h

ADC_CONTROL

01h

ADC_DATA_1

02h ADC_CONFIG_1A

03h ADC_CONFIG_1B

ADC

04h

ADC_DATA_2

05h ADC_CONFIG_2A

06h ADC_CONFIG_2B

07h

ADC_DATA_T

08h ADC_CONFIG_TA

09h ADC_CONFIG_TB

Figure 4. ADC Module

The four analog inputs (INP1, INM1, INP2, INM2) and

several internal circuit nodes can be multiplexed to the

ADC for a single-ended conversion relative to VSS. The

selection of which circuit node is multiplexed to the ADC

is controlled by the ADC_Control register. The ADC can

measure each of the op-amp output nodes with gain for

converting user-defined circuits or incorporating system

diagnostic test functions. The DAC outputs can be con-

verted by the ADC with either op amp arranged as

unity-gain buffers on the DAC outputs. The internal

power nodes, VDD and VSS, and the bandgap reference

VBG can be multiplexed to the ADC for conversion as

well. These measurement modes are defined and initiat-

ed in the ADC_Control register. See Tables 5 and 7 for

the single-ended configuration.

ADC Registers

The ADC module has 10 registers for configuration,

control, and data output. There are three conversion

channels in the ADC; channel 1, channel 2, and tem-

perature. Channels 1 and 2 are associated with the dif-

ferential signal input pairs INP1-INM1 and INP2-INM2,

respectively. The temperature channel is associated

with the integrated temperature sensor. Each channel

has two configuration registers (ADC_Config_nA and

ADC_Config_nB where n = 1, 2, or T) for setting con-

version resolution, reference input, coarse offsets, etc.

The data output from a conversion of channel 1, 2, or T

is stored in the respective data output register

ADC_Data_n where n = 1, 2, or T. Each of the channels

can be used to convert single-ended inputs as listed in

Table 7. The ADC_Control register controls which chan-

nel is to be converted and what single-ended input, if

any, is to be directed to that channel.

Conversion Start

To initiate an ADC conversion, a word is written to the

ADC_Control register with either CNVT1, CNVT2, or

CNVTT bit set to a 1 (Table 6). When an ADC conver-

sion is initiated, the CPU is halted and all CPU and

FLASH activities cease. All CNVT1, CNVT2, and CNVTT

bits are cleared after the ADC conversion is completed.

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