DS89C420_05 Datasheet, PDF (7/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
Note 1:
The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/
maximum external clock speed. The term “1/tCLCL” used in the AC Characteristics variable timing table is determined from the
following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot
exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed.
4X/2X
CD1
CD0
1
0
0
0
0
0
X
0
1
X
1
0
X
1
1
Number of External Clock
Cycles per System Clock
(1/tCLCL)
1/4
1/2
Reserved
1
1024
External Clock Speed
Min
Max
5MHz
10MHz
—
See AC Characteristics
See AC Characteristics
8.25MHz
16.5MHz
—
See AC Characteristics
See AC Characteristics
Note 2: External MOVX instruction times are dependent on the setting of the MD2, MD1, and MD0 bits in the clock control register. The terms
“tSTC1, tSTC2, tSTC3” used in the variable timing table are calculated through the use of the table given below.
MD2
0
0
0
0
1
1
1
1
MD1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
MOVX INSTRUCTION TIME
(MACHINE CYCLES)
2
3
4
5
9
10
11
12
tSTC1
(tCLCL)
0
2
6
10
14
18
22
26
tSTC2
(tCLCL)
0
1
1
1
5
5
5
5
tSTC3
(tCLCL)
0
0
0
0
4
4
4
4
tSTC4
(tCLCL)
0
0
0
0
1
1
1
1
tSTC5
(tCLCL)
0
1
1
1
1
1
1
1
Note 3: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load
capacitance is dependent on the frequency of the selected crystal.
Figure 1. Non-Page Mode Timing
XTAL1
ALE
PSEN
RD
WR
Port 0
Port 2
tCLCL
tAVLL2
tAVLL
tLLPL
tPXIX
tLLIV
tLLAX
LSB
MOVX
tPXIZ
MSB
tLHLL
tAVLL3
tLLAX3
tLLAX2
tPLPH
tPLIV
tRLRH
tAVDV0
tLLDV
tAVIV0
tRLDV
LSB
MOVX
tAVWL2
MSB
LSB
DATA
tAVDV2
MSB
tPLAZ
tRHDX
tRHDZ
LSB
tAVWL0
OPCODE
tAVIV2
MSB
tWHLH
tLLWL
tWLWH
tWHQX
tQVWX
LSB
DATA
MSB
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