DS89C420_05 Datasheet, PDF (36/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
timer/counters without auto-reload. Each timer can also be used as a counter of external pulses on the
corresponding T0/T1 pin for 1-to-0 transitions. The timer mode (TMOD) register controls the operation mode. Each
timer consists of a 16-bit register in 2 bytes, which can be found in the SFR map as TL0, TH0, TL1, and TH1. The
timer control (TCON) register enables Timers 0 and 1.
Table 12. Timer Functions
FUNCTIONS
Timer/Counter
TIMER 0
13/16/8^*/2 x 8 bit
Timer with Capture
No
External Control-Pulse Counter
Yes
Up/Down Auto-Reload Timer/Counter
No
Baud Rate Generator
No
Timer-Output Clock Generator
No
*8-bit timer/counter includes auto-reload feature; 2- x 8-bit mode does not.
TIMER 1
13/16/8^* bit
No
Yes
No
Yes
No
TIMER 2
16 bit
Yes
No
Yes
Yes
Yes
Timer 2 is a true 16-bit timer/counter that, with a 16-bit capture (RCAP2L and RCAP2H) register, is able to provide
some unique functions like up/down auto-reload timer/counter and timer-output clock generation. Timer 2 (registers
TL2 and TH2) is enabled by the T2CON register, and its mode of operation is selected by the T2MOD register.
Each timer has a selectable time base (Table 14). Following a reset, the timers default to divide-by-12 to maintain
drop-in compatible with the 8051. If Timer 2 is used as a baud rate generator or clock output, its time base is fixed
at divide by 2, regardless of the setting of its timer mode bits.
For details of operation, refer to “Programmable Timers” in the Ultra-High-Speed Flash Microcontroller User’s
Guide.
TIMED ACCESS
The timed access function provides control verification to system functions. The timed access function prevents an
errant CPU from making accidental changes to certain SFR bits that are considered vital to proper system
operation. This is achieved by using software control when accessing the following SFR control bits:
WDCON.0
RWT
Reset Watchdog Timer
WDCON.1
EWT
Watchdog Reset Enable
WDCON.3
WDIF
Watchdog Interrupt Flag
WDCON.6
POR
Power-On Reset Flag
EXIF.0
BGS
Bandgap Select
ACON.5
PAGES0 Page Mode Select Bit 0
ACON.6
PAGES1 Page Mode Select Bit 1
ACON.7
PAGEE
Page Mode Enable
ROMSIZE.0
RMS0
Program Memory Size Select Bit 0
ROMSIZE.1
RMS1
Program Memory Size Select Bit 1
ROMSIZE.2
RMS2
Program Memory Size Select Bit 2
ROMSIZE.3
PRAME
Program RAM Enable
FCNTL.0 FC0
Flash Command Bit 0
FCNTL.1 FC1
Flash Command Bit 1
FCNTL.2 FC2
Flash Command Bit 2
FCNTL.3 FC3
Flash Command Bit 3
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