DS89C420_05 Datasheet, PDF (29/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b:
§ PSEN is asserted for both page hit and page miss for a full clock cycle.
§ The execution of external MOVX instruction causes a page miss.
§ A page miss occurs when fetching the next external instruction following the execution of an external MOVX
instruction.
Figure 11 shows the external memory cycle for this bus structure. The first case illustrates a back-to-back
execution sequence for 1-cycle page mode (PAGES1 = PAGES0 = 0b). PSEN remains active during page-hit
cycles, and page misses are forced during and after MOVX executions, independent of the most significant byte of
the subsequent addresses. The second case illustrates a MOVX execution sequence for 2-cycle page mode
(PAGES1 = 0 and PAGES0 = 1). PSEN is active for a full clock cycle in code fetches. Note that changing the MSB
of the data address causes the page misses in this sequence. The third case illustrates a MOVX execution
sequence for 4-cycle page mode (PAGES1 = 1 and PAGES0 = 0). There is no page miss in this execution cycle
because the most significant byte of the data address is assumed to match the last program address.
The second page mode (page mode 2) external bus structure multiplexes the most significant address byte with
data on P2, and uses P0 for the least significant address byte. This bus structure is used to speed up external code
fetches only. External data-memory access cycles are identical to the non-page mode except for the different
signals on P0 and P2. Figure 12 illustrates the memory cycle for external code fetches.
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