DS89C420_05 Datasheet, PDF (28/47 Pages) Maxim Integrated Products – Ultra-High-Speed Microcontroller

DS89C420 Ultra-High-Speed Microcontroller
PAGE MODE, EXTERNAL MEMORY CYCLE
Page mode retains the basic circuitry requirement for original 8051 external memory interface, but alters the
configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles.
Additionally, the functions of ALE and PSEN are altered to support this mode of operation.
Setting the PAGEE (ACON.7) bit to logic 1 enables page mode. Clearing the PAGEE bit to a logic 0 disables the
page mode and the external bus structure defaults to the original 8051 expanded bus configuration (non-page
mode). The DS89C420 supports page mode in two external bus structures. The logic value of the page mode
select bits in the ACON register determines the external bus structure and the basic memory cycle in the number of
system clocks. Table 6 summarizes this option. The first three selections use the same bus structure but with a
different memory cycle time. Setting the select bits to 11b selects another bus structure. Write access to the ACON
register requires a timed access.
Table 6. Page Mode Select
PAGES1:PAGES0
00
01
10
11
CLOCKS PER MEMORY CYCLE
PAGE HIT
PAGE MISS
1
2
2
4
4
8
2
4
EXTERNAL BUS STRUCTURE
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of the address.
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of the address.
P0: Primary data bus.
P2: Primary address bus, multiplexing both the upper byte and
lower byte of the address.
P0: Lower address byte.
P2: The upper address byte is multiplexed with the data byte.
Note: This setting affects external code fetches only; accessing the
external data memory requires 4 clock cycles, regardless of page hit
or miss.
The first page mode (page mode 1) external bus structure uses P2 as the primary address bus, (multiplexing both
the most significant byte (MSB) and least significant byte (LSB) of the address for each external memory cycle) and
P0 is used as the primary data bus. During external code fetches, P0 is held in a high-impedance state by the
processor. Op codes are driven by the external memory onto P0 and latched at the end of the external fetch cycle
at the rising edge of PSEN. During external data read/write operations, P0 functions as the data I/O bus. It is held in
a high-impedance state for external reads from data memory, and driven with data during external writes to data
memory.
§ A page miss occurs when the MSB of the subsequent address is different from the last address. The external
memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss.
§ A page hit occurs when the MSB of the subsequent address does not change from the last address. The
external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit.
During a page hit, P2 drives Addr0–7 of the 16-bit address while the most significant address byte is held in the
external address latches. PSEN, RD, and WR strobe accordingly for the appropriate operation on the P0 data bus.
There is no ALE assertion for page hits.
During a page miss, P2 drives the Addr [8:15] of the 16-bit address and holds it for the duration of the first half of
the memory cycle to allow the external address latches to latch the new most significant address byte. ALE is
asserted to strobe the external address latches. During this operation, PSEN, RD, and WR are held in inactive
states and P0 is in a high-impedance state. The second half of the memory cycle is executed as a page-hit cycle
and the appropriate operation takes place.
A page miss can occur at set intervals or during external operations that require a memory access into a page of
memory that has not been accessed during the last external cycle. Generally, the first external memory access
causes a page miss. The new page address is stored internally, and is used to detect a page miss for the current
external memory cycle.
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